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adding another important port combination to unit tests

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Michael Timothy Grimes
2018-06-03 19:36:48 -07:00
parent fea304eac1
commit d7a024b8fc
2 changed files with 8 additions and 0 deletions
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compiler/tests/04_pbitcell_1X_test.py
+4
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@@ -42,6 +42,10 @@ class pbitcell_test(openram_test):
debug.info(2, "Bitcell with 0 read ports")
tx = pbitcell.pbitcell(num_readwrite=1,num_write=1,num_read=0)
self.local_check(tx)
debug.info(2, "Bitcell with 0 read ports and 0 write ports")
tx = pbitcell.pbitcell(num_readwrite=1,num_write=0,num_read=0)
self.local_check(tx)
OPTS.check_lvsdrc = True
globals.end_openram()
compiler/tests/04_pbitcell_test.py
+4
View File
@@ -42,6 +42,10 @@ class pbitcell_test(openram_test):
debug.info(2, "Bitcell with 0 read ports")
tx = pbitcell.pbitcell(num_readwrite=2,num_write=2,num_read=0)
self.local_check(tx)
debug.info(2, "Bitcell with 0 read ports and 0 write ports")
tx = pbitcell.pbitcell(num_readwrite=2,num_write=0,num_read=0)
self.local_check(tx)
OPTS.check_lvsdrc = True
globals.end_openram()