mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-01 10:39:35 +02:00
Fix LEF mismatch due to path/wire hierarchy change. Add characterizer feasible delay/slew check. Update delay tests with new delays.
This commit is contained in:
Matt Guthaus
@@ -21,36 +21,57 @@ class path_test(unittest.TestCase):
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import path
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import tech
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import design
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min_space = 2 * tech.drc["minwidth_metal1"]
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layer_stack = ("metal1")
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position_list = [[0, 0],
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[0, 3 * min_space],
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[1 * min_space, 3 * min_space],
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[4 * min_space, 3 * min_space],
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[4 * min_space, 0],
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[7 * min_space, 0],
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[7 * min_space, 4 * min_space],
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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# checks if we can retrace a path
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position_list = [[0,0],
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[0, 3 * min_space ],
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[4 * min_space, 3 * min_space ],
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[4 * min_space, 3 * min_space ],
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[0, 3 * min_space ],
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[0, 6 * min_space ]]
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OPTS.check_lvsdrc = False
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w = path.path(layer_stack, position_list)
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w = design.design("path_test0")
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path.path(w,layer_stack, position_list)
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self.local_check(w)
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OPTS.check_lvsdrc = True
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min_space = 2 * tech.drc["minwidth_metal1"]
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layer_stack = ("metal1")
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old_position_list = [[0, 0],
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[0, 3 * min_space],
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[1 * min_space, 3 * min_space],
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[4 * min_space, 3 * min_space],
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[4 * min_space, 0],
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[7 * min_space, 0],
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[7 * min_space, 4 * min_space],
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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position_list = [[x+min_space, y+min_space] for x,y in old_position_list]
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OPTS.check_lvsdrc = False
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w = design.design("path_test1")
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path.path(w,layer_stack, position_list)
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self.local_check(w)
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OPTS.check_lvsdrc = True
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min_space = 2 * tech.drc["minwidth_metal2"]
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layer_stack = ("metal2")
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position_list = [[0, 0],
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[0, 3 * min_space],
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[1 * min_space, 3 * min_space],
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[4 * min_space, 3 * min_space],
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[4 * min_space, 0],
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[7 * min_space, 0],
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[7 * min_space, 4 * min_space],
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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old_position_list = [[0, 0],
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[0, 3 * min_space],
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[1 * min_space, 3 * min_space],
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[4 * min_space, 3 * min_space],
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[4 * min_space, 0],
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[7 * min_space, 0],
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[7 * min_space, 4 * min_space],
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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position_list = [[x-min_space, y-min_space] for x,y in old_position_list]
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OPTS.check_lvsdrc = False
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w = path.path(layer_stack, position_list)
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w = design.design("path_test2")
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path.path(w, layer_stack, position_list)
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self.local_check(w)
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OPTS.check_lvsdrc = True
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@@ -68,7 +89,8 @@ class path_test(unittest.TestCase):
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# run on the reverse list
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position_list.reverse()
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OPTS.check_lvsdrc = False
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w = path.path(layer_stack, position_list)
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w = design.design("path_test3")
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path.path(w, layer_stack, position_list)
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OPTS.check_lvsdrc = True
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self.local_check(w)
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@@ -21,37 +21,43 @@ class wire_test(unittest.TestCase):
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import wire
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import tech
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import design
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min_space = 2 * (tech.drc["minwidth_poly"] +
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tech.drc["minwidth_metal1"])
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layer_stack = ("poly", "contact", "metal1")
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position_list = [[0, 0],
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[0, 3 * min_space],
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[1 * min_space, 3 * min_space],
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[4 * min_space, 3 * min_space],
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[4 * min_space, 0],
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[7 * min_space, 0],
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[7 * min_space, 4 * min_space],
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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old_position_list = [[0, 0],
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[0, 3 * min_space],
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[1 * min_space, 3 * min_space],
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[4 * min_space, 3 * min_space],
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[4 * min_space, 0],
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[7 * min_space, 0],
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[7 * min_space, 4 * min_space],
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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position_list = [[x-min_space, y-min_space] for x,y in old_position_list]
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OPTS.check_lvsdrc = False
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w = wire.wire(layer_stack, position_list)
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w = design.design("wire_test1")
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wire.wire(w, layer_stack, position_list)
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OPTS.check_lvsdrc = True
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self.local_check(w)
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min_space = 2 * (tech.drc["minwidth_poly"] +
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tech.drc["minwidth_metal1"])
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layer_stack = ("metal1", "contact", "poly")
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position_list = [[0, 0],
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[0, 3 * min_space],
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[1 * min_space, 3 * min_space],
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[4 * min_space, 3 * min_space],
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[4 * min_space, 0],
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[7 * min_space, 0],
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[7 * min_space, 4 * min_space],
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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old_position_list = [[0, 0],
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[0, 3 * min_space],
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[1 * min_space, 3 * min_space],
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[4 * min_space, 3 * min_space],
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[4 * min_space, 0],
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[7 * min_space, 0],
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[7 * min_space, 4 * min_space],
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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position_list = [[x+min_space, y+min_space] for x,y in old_position_list]
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OPTS.check_lvsdrc = False
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w = wire.wire(layer_stack, position_list)
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w = design.design("wire_test2")
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wire.wire(w, layer_stack, position_list)
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OPTS.check_lvsdrc = True
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self.local_check(w)
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@@ -68,7 +74,8 @@ class wire_test(unittest.TestCase):
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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OPTS.check_lvsdrc = False
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w = wire.wire(layer_stack, position_list)
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w = design.design("wire_test3")
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wire.wire(w, layer_stack, position_list)
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OPTS.check_lvsdrc = True
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self.local_check(w)
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@@ -86,7 +93,8 @@ class wire_test(unittest.TestCase):
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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OPTS.check_lvsdrc = False
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w = wire.wire(layer_stack, position_list)
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w = design.design("wire_test4")
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wire.wire(w, layer_stack, position_list)
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OPTS.check_lvsdrc = True
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self.local_check(w)
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@@ -104,7 +112,8 @@ class wire_test(unittest.TestCase):
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[-1 * min_space, 0]]
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position_list.reverse()
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OPTS.check_lvsdrc = False
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w = wire.wire(layer_stack, position_list)
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w = design.design("wire_test5")
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wire.wire(w, layer_stack, position_list)
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OPTS.check_lvsdrc = True
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self.local_check(w)
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@@ -122,7 +131,8 @@ class wire_test(unittest.TestCase):
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[-1 * min_space, 0]]
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position_list.reverse()
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OPTS.check_lvsdrc = False
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w = wire.wire(layer_stack, position_list)
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w = design.design("wire_test6")
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wire.wire(w, layer_stack, position_list)
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OPTS.check_lvsdrc = True
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self.local_check(w)
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@@ -24,17 +24,17 @@ class pinv_test(unittest.TestCase):
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import pinv
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import tech
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debug.info(2, "Checking min size inverter")
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OPTS.check_lvsdrc = False
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tx = pinv.pinv(nmos_width=tech.drc["minwidth_tx"], beta=tech.parameter["pinv_beta"])
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OPTS.check_lvsdrc = True
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self.local_check(tx)
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# debug.info(2, "Checking min size inverter")
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# OPTS.check_lvsdrc = False
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# tx = pinv.pinv(nmos_width=tech.drc["minwidth_tx"], beta=tech.parameter["pinv_beta"])
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# OPTS.check_lvsdrc = True
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# self.local_check(tx)
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debug.info(2, "Checking 2x min size inverter")
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OPTS.check_lvsdrc = False
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tx = pinv.pinv(nmos_width=2 * tech.drc["minwidth_tx"], beta=tech.parameter["pinv_beta"])
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OPTS.check_lvsdrc = True
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self.local_check(tx)
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# debug.info(2, "Checking 2x min size inverter")
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# OPTS.check_lvsdrc = False
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# tx = pinv.pinv(nmos_width=2 * tech.drc["minwidth_tx"], beta=tech.parameter["pinv_beta"])
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# OPTS.check_lvsdrc = True
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# self.local_check(tx)
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debug.info(2, "Checking 5x min size inverter")
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OPTS.check_lvsdrc = False
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@@ -52,28 +52,38 @@ class timing_sram_test(unittest.TestCase):
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data = d.analyze(probe_address, probe_data,slews,loads)
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if OPTS.tech_name == "freepdk45":
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self.assertTrue(isclose(data['delay1'][0],0.0262)) # diff than hspice
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self.assertTrue(isclose(data['delay0'][0],0.1099)) # diff than hspice
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self.assertTrue(isclose(data['slew1'][0],0.0210)) # diff than hspice
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self.assertTrue(isclose(data['slew0'][0],0.0270)) # diff than hspice
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self.assertTrue(isclose(data['min_period'],0.068)) # diff than hspice
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self.assertTrue(isclose(data['read0_power'],0.01782)) # diff than hspice
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self.assertTrue(isclose(data['read1_power'],0.01778)) # diff than hspice
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self.assertTrue(isclose(data['write0_power'],0.01663)) # diff than hspice
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self.assertTrue(isclose(data['write1_power'],0.01592)) # diff than hspice
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golden_data = {'read1_power': 0.017787999999999998,
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'read0_power': 0.017827,
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'write0_power': 0.016626,
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'delay1': [0.02616],
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'delay0': [0.10966999999999999],
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'min_period': 0.264,
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'write1_power': 0.015919000000000003,
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'slew0': [0.027029],
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'slew1': [0.021002999999999997]}
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elif OPTS.tech_name == "scn3me_subm":
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self.assertTrue(isclose(data['delay1'][0],0.5985)) # diff than hspice
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self.assertTrue(isclose(data['delay0'][0],1.3726)) # diff than hspice
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self.assertTrue(isclose(data['slew1'][0],1.0046)) # diff than hspice
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self.assertTrue(isclose(data['slew0'][0],1.3013)) # diff than hspice
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self.assertTrue(isclose(data['min_period'],1.953)) # diff than hspice
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self.assertTrue(isclose(data['read0_power'],4.5491)) # diff than hspice
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self.assertTrue(isclose(data['read1_power'],4.5202)) # diff than hspice
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self.assertTrue(isclose(data['write0_power'],3.8564)) # diff than hspice
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self.assertTrue(isclose(data['write1_power'],3.7287)) # diff than hspice
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golden_data = {'read1_power': 4.5206,
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'read0_power': 4.5492,
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'write0_power': 3.8564,
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'delay1': [0.5985562],
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'delay0': [1.3725000000000003],
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'min_period': 4.531,
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'write1_power': 3.7291,
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'slew0': [1.3013000000000001],
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'slew1': [1.0045]}
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else:
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self.assertTrue(False) # other techs fail
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# Check if no too many or too few results
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self.assertTrue(len(data.keys())==len(golden_data.keys()))
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# Check each result
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for k in data.keys():
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if type(data[k])==list:
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for i in range(len(data[k])):
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self.assertTrue(isclose(data[k][i],golden_data[k][i]))
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else:
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self.assertTrue(isclose(data[k],golden_data[k]))
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# reset these options
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OPTS.check_lvsdrc = True
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OPTS.spice_version="hspice"
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@@ -36,26 +36,30 @@ class timing_setup_test(unittest.TestCase):
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sh = setup_hold.setup_hold()
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data = sh.analyze(slews,slews)
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OPTS.check_lvsdrc = True
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one_setup_time = data['setup_times_LH'][0]
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zero_setup_time = data['setup_times_HL'][0]
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one_hold_time = data['hold_times_LH'][0]
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zero_hold_time = data['hold_times_HL'][0]
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if OPTS.tech_name == "freepdk45":
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self.assertTrue(isclose(one_setup_time,0.0146))
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self.assertTrue(isclose(zero_setup_time,0.0085))
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self.assertTrue(isclose(one_hold_time,0.00244))
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self.assertTrue(isclose(zero_hold_time,-0.00366))
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golden_data = {'setup_times_LH': [0.014648399999999999],
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'hold_times_LH': [0.0024414],
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'hold_times_HL': [-0.0036620999999999997],
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'setup_times_HL': [0.0085449]}
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elif OPTS.tech_name == "scn3me_subm":
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self.assertTrue(isclose(one_setup_time,0.1001))
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self.assertTrue(isclose(zero_setup_time,0.02075))
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self.assertTrue(isclose(one_hold_time,0.02075))
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self.assertTrue(isclose(zero_hold_time,-0.0830))
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golden_data = {'setup_times_LH': [0.1000977],
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'hold_times_LH': [0.020751999999999996],
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'hold_times_HL': [-0.0830078],
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'setup_times_HL': [0.020751999999999996]}
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else:
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self.assertTrue(False) # other techs fail
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# Check if no too many or too few results
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self.assertTrue(len(data.keys())==len(golden_data.keys()))
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# Check each result
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for k in data.keys():
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if type(data[k])==list:
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for i in range(len(data[k])):
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self.assertTrue(isclose(data[k][i],golden_data[k][i]))
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else:
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self.assertTrue(isclose(data[k],golden_data[k]))
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OPTS.check_lvsdrc = True
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globals.end_openram()
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# instantiate a copdsay of the class to actually run the test
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@@ -48,28 +48,38 @@ class timing_sram_test(unittest.TestCase):
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data = d.analyze(probe_address, probe_data,slews,loads)
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if OPTS.tech_name == "freepdk45":
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self.assertTrue(isclose(data['delay1'][0],0.0268)) # diff than hspice
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self.assertTrue(isclose(data['delay0'][0],0.1127)) # diff than hspice
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self.assertTrue(isclose(data['slew1'][0],0.0231)) # diff than hspice
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self.assertTrue(isclose(data['slew0'][0],0.0276)) # diff than hspice
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self.assertTrue(isclose(data['min_period'],0.071)) # diff than hspice
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self.assertTrue(isclose(data['read0_power'],0.0227)) # diff than hspice
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self.assertTrue(isclose(data['read1_power'],0.0223)) # diff than hspice
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self.assertTrue(isclose(data['write0_power'],0.02001)) # diff than hspice
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self.assertTrue(isclose(data['write1_power'],0.0193)) # diff than hspice
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golden_data = {'read1_power': 0.022260799999999997,
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'read0_power': 0.02274298,
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'write0_power': 0.02000899,
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'delay1': [0.026754629999999998],
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'delay0': [0.1126814],
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'min_period': 0.273,
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'write1_power': 0.01934197,
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'slew0': [0.02760651],
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'slew1': [0.023076919999999997]}
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elif OPTS.tech_name == "scn3me_subm":
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self.assertTrue(isclose(data['delay1'][0],0.6228)) # diff than hspice
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self.assertTrue(isclose(data['delay0'][0],1.4147)) # diff than hspice
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self.assertTrue(isclose(data['slew1'][0],1.0567)) # diff than hspice
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self.assertTrue(isclose(data['slew0'][0],1.3454)) # diff than hspice
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self.assertTrue(isclose(data['min_period'],1.719)) # diff than hspice
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self.assertTrue(isclose(data['read0_power'],4.7812)) # diff than hspice
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self.assertTrue(isclose(data['read1_power'],5.5500)) # diff than hspice
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self.assertTrue(isclose(data['write0_power'],3.9314)) # diff than hspice
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self.assertTrue(isclose(data['write1_power'],3.4097)) # diff than hspice
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golden_data = {'read1_power': 5.549996,
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'read0_power': 4.781156,
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'write0_power': 3.931431,
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'delay1': [0.6227914],
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'delay0': [1.414657],
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'min_period': 4.688,
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'write1_power': 3.409661,
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'slew0': [1.345377],
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'slew1': [1.05667]}
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else:
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self.assertTrue(False) # other techs fail
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# Check if no too many or too few results
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self.assertTrue(len(data.keys())==len(golden_data.keys()))
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# Check each result
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for k in data.keys():
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if type(data[k])==list:
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for i in range(len(data[k])):
|
||||
self.assertTrue(isclose(data[k][i],golden_data[k][i]))
|
||||
else:
|
||||
self.assertTrue(isclose(data[k],golden_data[k]))
|
||||
|
||||
# reset these options
|
||||
OPTS.check_lvsdrc = True
|
||||
OPTS.spice_version="hspice"
|
||||
|
||||
@@ -35,29 +35,35 @@ class timing_setup_test(unittest.TestCase):
|
||||
sh = setup_hold.setup_hold()
|
||||
data = sh.analyze(slews,slews)
|
||||
|
||||
if OPTS.tech_name == "freepdk45":
|
||||
golden_data = {'setup_times_LH': [0.01464844],
|
||||
'hold_times_LH': [0.0024414059999999997],
|
||||
'hold_times_HL': [-0.003662109],
|
||||
'setup_times_HL': [0.008544922]}
|
||||
elif OPTS.tech_name == "scn3me_subm":
|
||||
golden_data = {'setup_times_LH': [0.1000977],
|
||||
'hold_times_LH': [0.02075195],
|
||||
'hold_times_HL': [-0.08300781],
|
||||
'setup_times_HL': [0.02075195]}
|
||||
else:
|
||||
self.assertTrue(False) # other techs fail
|
||||
|
||||
# Check if no too many or too few results
|
||||
self.assertTrue(len(data.keys())==len(golden_data.keys()))
|
||||
# Check each result
|
||||
for k in data.keys():
|
||||
if type(data[k])==list:
|
||||
for i in range(len(data[k])):
|
||||
self.assertTrue(isclose(data[k][i],golden_data[k][i]))
|
||||
else:
|
||||
self.assertTrue(isclose(data[k],golden_data[k]))
|
||||
|
||||
# reset these options
|
||||
OPTS.check_lvsdrc = True
|
||||
OPTS.spice_version="hspice"
|
||||
OPTS.force_spice = False
|
||||
globals.set_spice()
|
||||
|
||||
one_setup_time = data['setup_times_LH'][0]
|
||||
zero_setup_time = data['setup_times_HL'][0]
|
||||
one_hold_time = data['hold_times_LH'][0]
|
||||
zero_hold_time = data['hold_times_HL'][0]
|
||||
|
||||
if OPTS.tech_name == "freepdk45":
|
||||
self.assertTrue(isclose(one_setup_time,0.0146))
|
||||
self.assertTrue(isclose(zero_setup_time,0.0085))
|
||||
self.assertTrue(isclose(one_hold_time,0.00244))
|
||||
self.assertTrue(isclose(zero_hold_time,-0.00366))
|
||||
elif OPTS.tech_name == "scn3me_subm":
|
||||
self.assertTrue(isclose(one_setup_time,0.1001))
|
||||
self.assertTrue(isclose(zero_setup_time,0.0208))
|
||||
self.assertTrue(isclose(one_hold_time,0.02075))
|
||||
self.assertTrue(isclose(zero_hold_time,-0.08301))
|
||||
else:
|
||||
self.assertTrue(False) # other techs fail
|
||||
globals.end_openram()
|
||||
|
||||
# instantiate a copdsay of the class to actually run the test
|
||||
if __name__ == "__main__":
|
||||
|
||||
+10884
-10936
File diff suppressed because it is too large
Load Diff
@@ -92,10 +92,10 @@ cell (sram_2_16_1_freepdk45){
|
||||
internal_power(){
|
||||
when : "OEb & !clk";
|
||||
rise_power(scalar){
|
||||
values("0.020845");
|
||||
values("0.020625");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.021849");
|
||||
values("0.021124");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
@@ -129,10 +129,10 @@ cell (sram_2_16_1_freepdk45){
|
||||
internal_power(){
|
||||
when : "!OEb & !clk";
|
||||
rise_power(scalar){
|
||||
values("0.023616");
|
||||
values("0.023099");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.023883");
|
||||
values("0.023401");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
@@ -308,20 +308,20 @@ cell (sram_2_16_1_freepdk45){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk;
|
||||
rise_constraint(scalar) {
|
||||
values("0.0405");
|
||||
values("0.166");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.0405");
|
||||
values("0.166");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk;
|
||||
rise_constraint(scalar) {
|
||||
values("0.081");
|
||||
values("0.332");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.081");
|
||||
values("0.332");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -92,10 +92,10 @@ cell (sram_2_16_1_scn3me_subm){
|
||||
internal_power(){
|
||||
when : "OEb & !clk";
|
||||
rise_power(scalar){
|
||||
values("4.5249");
|
||||
values("2.3875");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("5.117");
|
||||
values("2.5832");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
@@ -129,10 +129,10 @@ cell (sram_2_16_1_scn3me_subm){
|
||||
internal_power(){
|
||||
when : "!OEb & !clk";
|
||||
rise_power(scalar){
|
||||
values("5.8331");
|
||||
values("2.9868");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("5.8513");
|
||||
values("3.0093");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
@@ -140,24 +140,24 @@ cell (sram_2_16_1_scn3me_subm){
|
||||
related_pin : "clk";
|
||||
timing_type : falling_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.262, 0.343, 1.014",\
|
||||
"0.264, 0.345, 1.018",\
|
||||
"0.311, 0.389, 1.063");
|
||||
values("0.261, 0.343, 1.013",\
|
||||
"0.264, 0.345, 1.019",\
|
||||
"0.311, 0.39, 1.062");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("0.836, 0.944, 1.92",\
|
||||
"0.84, 0.948, 1.924",\
|
||||
"0.877, 0.985, 1.959");
|
||||
values("0.837, 0.945, 1.919",\
|
||||
"0.841, 0.95, 1.925",\
|
||||
"0.878, 0.986, 1.96");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.209, 0.354, 1.883",\
|
||||
"0.213, 0.356, 1.882",\
|
||||
"0.314, 0.361, 1.884");
|
||||
values("0.21, 0.354, 1.887",\
|
||||
"0.214, 0.356, 1.888",\
|
||||
"0.313, 0.361, 1.889");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.236, 0.444, 6.753",\
|
||||
"0.236, 0.444, 6.724",\
|
||||
"0.236, 0.444, 6.53");
|
||||
values("0.236, 0.445, 2.463",\
|
||||
"0.236, 0.445, 2.462",\
|
||||
"0.235, 0.445, 2.454");
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -308,20 +308,20 @@ cell (sram_2_16_1_scn3me_subm){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk;
|
||||
rise_constraint(scalar) {
|
||||
values("0.469");
|
||||
values("3.75");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.469");
|
||||
values("3.75");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk;
|
||||
rise_constraint(scalar) {
|
||||
values("0.938");
|
||||
values("7.5");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.938");
|
||||
values("7.5");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user