mirror of https://github.com/VLSIDA/OpenRAM.git
Update golden results for FreePDK45 tests.
This commit is contained in:
Matt Guthaus
parent
642a5cfe73
commit
d75d17bc8a
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@ -51,16 +51,16 @@ class timing_sram_test(openram_test):
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data = d.analyze(probe_address, probe_data, slews, loads)
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if OPTS.tech_name == "freepdk45":
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golden_data = {'leakage_power': 0.0006964536000000001,
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'delay_lh': [0.0573055],
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'read0_power': [0.0337812],
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'read1_power': [0.032946500000000004],
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'write1_power': [0.0361529],
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'write0_power': [0.026179099999999997],
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'slew_hl': [0.0285185],
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'min_period': 0.205,
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'delay_hl': [0.070554],
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'slew_lh': [0.0190073]}
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golden_data = {'delay_hl': [2.5614],
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'delay_lh': [0.22929839999999999],
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'leakage_power': 0.0020326,
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'min_period': 4.844,
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'read0_power': [0.0497676],
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'read1_power': [0.0463576],
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'slew_hl': [0.1119293],
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'slew_lh': [0.0237043],
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'write0_power': [0.0494321],
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'write1_power': [0.0457268]}
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elif OPTS.tech_name == "scn3me_subm":
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golden_data = {'delay_hl': [6.473300000000001],
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'delay_lh': [1.0442000000000002],
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@ -50,16 +50,16 @@ class timing_sram_test(openram_test):
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data = d.analyze(probe_address, probe_data, slews, loads)
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if OPTS.tech_name == "freepdk45":
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golden_data = {'leakage_power': 0.0007348262,
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'delay_lh': [0.05799613],
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'read0_power': [0.0384102],
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'read1_power': [0.03279848],
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'write1_power': [0.03693655],
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'write0_power': [0.02717752],
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'slew_hl': [0.03607912],
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'min_period': 0.742,
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'delay_hl': [0.3929995],
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'slew_lh': [0.02160862]}
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golden_data = {'delay_hl': [2.562671],
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'delay_lh': [0.2320771],
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'leakage_power': 0.00102373,
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'min_period': 4.844,
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'read0_power': [0.047404110000000006],
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'read1_power': [0.0438884],
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'slew_hl': [0.1140206],
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'slew_lh': [0.02492785],
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'write0_power': [0.04765188],
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'write1_power': [0.04434999]}
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elif OPTS.tech_name == "scn3me_subm":
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golden_data = {'delay_hl': [11.69536],
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'delay_lh': [1.260921],
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@ -78,27 +78,31 @@ cell (sram_2_16_1_freepdk45){
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dont_use : true;
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map_only : true;
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dont_touch : true;
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area : 1032.3999375;
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area : 948.52275;
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leakage_power () {
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when : "CSb";
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value : 0.0008128352;
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value : 0.0021292;
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}
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cell_leakage_power : 0;
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bus(DATA){
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bus(DIN){
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bus_type : DATA;
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direction : inout;
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direction : in;
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max_capacitance : 1.6728;
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min_capacitance : 0.052275;
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three_state : "!OEb & !clk";
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memory_write(){
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address : ADDR;
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clocked_on : clk;
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}
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bus(DOUT){
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bus_type : DATA;
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direction : out;
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max_capacitance : 1.6728;
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min_capacitance : 0.052275;
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memory_read(){
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address : ADDR;
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}
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pin(DATA[1:0]){
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pin(DOUT[1:0]){
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timing(){
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timing_type : setup_rising;
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related_pin : "clk";
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@ -130,26 +134,26 @@ cell (sram_2_16_1_freepdk45){
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timing(){
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timing_sense : non_unate;
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related_pin : "clk";
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timing_type : falling_edge;
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timing_type : rising_edge;
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cell_rise(CELL_TABLE) {
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values("0.055, 0.056, 0.063",\
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"0.056, 0.057, 0.063",\
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"0.061, 0.062, 0.069");
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values("0.229, 0.23, 0.234",\
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"0.23, 0.23, 0.234",\
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"0.236, 0.236, 0.24");
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}
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cell_fall(CELL_TABLE) {
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values("0.067, 0.068, 0.076",\
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"0.067, 0.068, 0.077",\
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"0.073, 0.074, 0.082");
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values("2.555, 2.556, 2.568",\
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"2.555, 2.557, 2.569",\
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"2.562, 2.563, 2.575");
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}
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rise_transition(CELL_TABLE) {
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values("0.013, 0.015, 0.026",\
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"0.013, 0.015, 0.026",\
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"0.014, 0.015, 0.026");
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values("0.02, 0.021, 0.028",\
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"0.02, 0.021, 0.028",\
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"0.02, 0.021, 0.028");
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}
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fall_transition(CELL_TABLE) {
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values("0.023, 0.024, 0.037",\
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"0.023, 0.024, 0.037",\
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"0.024, 0.024, 0.037");
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values("0.111, 0.112, 0.115",\
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"0.111, 0.111, 0.115",\
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"0.111, 0.111, 0.116");
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}
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}
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}
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@ -298,19 +302,19 @@ cell (sram_2_16_1_freepdk45){
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internal_power(){
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when : "!CSb & clk & !WEb";
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rise_power(scalar){
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values("0.0175059861111");
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values("0.027431397222222223");
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}
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fall_power(scalar){
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values("0.0175059861111");
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values("0.027431397222222223");
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}
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}
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internal_power(){
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when : "!CSb & !clk & WEb";
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rise_power(scalar){
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values("0.0218644166667");
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values("0.026240397222222222");
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}
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fall_power(scalar){
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values("0.0218644166667");
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values("0.026240397222222222");
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}
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}
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internal_power(){
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@ -326,20 +330,20 @@ cell (sram_2_16_1_freepdk45){
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timing_type :"min_pulse_width";
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related_pin : clk;
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rise_constraint(scalar) {
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values("0.117");
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values("2.422");
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}
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fall_constraint(scalar) {
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values("0.117");
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values("2.422");
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}
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}
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timing(){
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timing_type :"minimum_period";
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related_pin : clk;
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rise_constraint(scalar) {
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values("0.234");
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values("4.844");
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}
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fall_constraint(scalar) {
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values("0.234");
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values("4.844");
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}
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}
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}
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@ -78,27 +78,31 @@ cell (sram_2_16_1_freepdk45){
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dont_use : true;
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map_only : true;
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dont_touch : true;
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area : 1032.3999375;
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area : 948.52275;
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leakage_power () {
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when : "CSb";
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value : 0.000173;
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value : 0.000168;
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}
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cell_leakage_power : 0;
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bus(DATA){
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bus(DIN){
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bus_type : DATA;
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direction : inout;
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direction : in;
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max_capacitance : 1.6728;
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min_capacitance : 0.052275;
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three_state : "!OEb & !clk";
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memory_write(){
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address : ADDR;
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clocked_on : clk;
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}
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bus(DOUT){
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bus_type : DATA;
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direction : out;
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max_capacitance : 1.6728;
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min_capacitance : 0.052275;
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memory_read(){
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address : ADDR;
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}
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pin(DATA[1:0]){
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pin(DOUT[1:0]){
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timing(){
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timing_type : setup_rising;
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related_pin : "clk";
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@ -130,16 +134,16 @@ cell (sram_2_16_1_freepdk45){
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timing(){
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timing_sense : non_unate;
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related_pin : "clk";
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timing_type : falling_edge;
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timing_type : rising_edge;
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cell_rise(CELL_TABLE) {
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values("0.123, 0.124, 0.133",\
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"0.123, 0.124, 0.133",\
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"0.123, 0.124, 0.133");
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values("0.103, 0.104, 0.113",\
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"0.103, 0.104, 0.113",\
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"0.103, 0.104, 0.113");
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}
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cell_fall(CELL_TABLE) {
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values("0.123, 0.124, 0.133",\
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"0.123, 0.124, 0.133",\
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"0.123, 0.124, 0.133");
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values("0.103, 0.104, 0.113",\
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"0.103, 0.104, 0.113",\
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"0.103, 0.104, 0.113");
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}
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rise_transition(CELL_TABLE) {
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values("0.006, 0.007, 0.018",\
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@ -298,19 +302,19 @@ cell (sram_2_16_1_freepdk45){
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internal_power(){
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when : "!CSb & clk & !WEb";
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rise_power(scalar){
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values("0.065526962224");
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values("0.0739870044551111");
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}
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fall_power(scalar){
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values("0.065526962224");
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values("0.0739870044551111");
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}
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}
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internal_power(){
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when : "!CSb & !clk & WEb";
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rise_power(scalar){
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values("0.065526962224");
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values("0.0739870044551111");
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}
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fall_power(scalar){
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values("0.065526962224");
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values("0.0739870044551111");
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}
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}
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internal_power(){
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@ -336,10 +340,10 @@ cell (sram_2_16_1_freepdk45){
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timing_type :"minimum_period";
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related_pin : clk;
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rise_constraint(scalar) {
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values("0.0");
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values("0");
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}
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fall_constraint(scalar) {
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values("0.0");
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values("0");
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}
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}
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}
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@ -78,27 +78,31 @@ cell (sram_2_16_1_freepdk45){
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dont_use : true;
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map_only : true;
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dont_touch : true;
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area : 1032.3999375;
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area : 948.52275;
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leakage_power () {
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when : "CSb";
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value : 0.0008128352;
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value : 0.0021292;
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}
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cell_leakage_power : 0;
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bus(DATA){
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bus(DIN){
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bus_type : DATA;
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direction : inout;
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direction : in;
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max_capacitance : 1.6728;
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min_capacitance : 0.052275;
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three_state : "!OEb & !clk";
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memory_write(){
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address : ADDR;
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clocked_on : clk;
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}
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bus(DOUT){
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bus_type : DATA;
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direction : out;
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max_capacitance : 1.6728;
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min_capacitance : 0.052275;
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memory_read(){
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address : ADDR;
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}
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pin(DATA[1:0]){
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pin(DOUT[1:0]){
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timing(){
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timing_type : setup_rising;
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related_pin : "clk";
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@ -130,26 +134,26 @@ cell (sram_2_16_1_freepdk45){
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timing(){
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timing_sense : non_unate;
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related_pin : "clk";
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timing_type : falling_edge;
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timing_type : rising_edge;
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cell_rise(CELL_TABLE) {
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values("0.054, 0.055, 0.061",\
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"0.055, 0.056, 0.062",\
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"0.06, 0.061, 0.068");
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values("0.227, 0.227, 0.231",\
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"0.227, 0.228, 0.232",\
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"0.233, 0.234, 0.238");
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}
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cell_fall(CELL_TABLE) {
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values("0.066, 0.067, 0.075",\
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"0.067, 0.068, 0.076",\
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"0.072, 0.073, 0.082");
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values("2.555, 2.557, 2.569",\
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"2.556, 2.557, 2.569",\
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"2.562, 2.563, 2.576");
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}
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rise_transition(CELL_TABLE) {
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values("0.013, 0.014, 0.026",\
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"0.013, 0.015, 0.026",\
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"0.013, 0.015, 0.026");
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values("0.02, 0.021, 0.028",\
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"0.02, 0.021, 0.028",\
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"0.02, 0.021, 0.028");
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}
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fall_transition(CELL_TABLE) {
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values("0.023, 0.024, 0.037",\
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"0.023, 0.024, 0.037",\
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"0.024, 0.024, 0.037");
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values("0.11, 0.11, 0.114",\
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"0.109, 0.11, 0.113",\
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"0.11, 0.11, 0.114");
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}
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}
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}
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@ -298,19 +302,19 @@ cell (sram_2_16_1_freepdk45){
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internal_power(){
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when : "!CSb & clk & !WEb";
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rise_power(scalar){
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values("0.0159801855389");
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values("0.025181683333333333");
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}
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fall_power(scalar){
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values("0.0159801855389");
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values("0.025181683333333333");
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}
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}
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internal_power(){
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when : "!CSb & !clk & WEb";
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rise_power(scalar){
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values("0.0171325605389");
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values("0.024945991666666667");
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}
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fall_power(scalar){
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values("0.0171325605389");
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values("0.024945991666666667");
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}
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}
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internal_power(){
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@ -326,20 +330,20 @@ cell (sram_2_16_1_freepdk45){
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timing_type :"min_pulse_width";
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related_pin : clk;
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rise_constraint(scalar) {
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values("0.1125");
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values("2.422");
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}
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fall_constraint(scalar) {
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values("0.1125");
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values("2.422");
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}
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}
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timing(){
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timing_type :"minimum_period";
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related_pin : clk;
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rise_constraint(scalar) {
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values("0.225");
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values("4.844");
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}
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fall_constraint(scalar) {
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values("0.225");
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values("4.844");
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}
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}
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}
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@ -79,7 +79,7 @@ class openram_test(unittest.TestCase):
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if not data_matches:
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import pprint
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data_string=pprint.pformat(data)
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debug.error("Data exceeded {:.1f}% tolerance:\n".format(error_tolerance*100)+data_string)
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debug.error("Results exceeded {:.1f}% tolerance compared to golden results:\n".format(error_tolerance*100)+data_string)
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return data_matches
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