mirror of https://github.com/VLSIDA/OpenRAM.git
Vdd/gnd via stacks now use perferred directions, added cell property to override
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1617840ed3
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@ -1201,10 +1201,16 @@ class layout():
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the given center location. The starting layer is specified to determine
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which vias are needed.
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"""
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# Force vdd/gnd via stack to be vertically or horizontally oriented
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# Default: None, uses prefered metal directions
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if vertical:
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direction = ("V", "V")
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else:
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elif not vertical and vertical is not None:
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direction = ("H", "H")
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else:
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direction = None
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via = self.add_via_stack_center(from_layer=start_layer,
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to_layer=self.pwr_grid_layer,
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@ -1390,4 +1396,3 @@ class layout():
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debug.info(0, "name={0} : mod={1} : offset={2}".format(inst.name,
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inst.mod.name,
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inst.offset))
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@ -101,13 +101,20 @@ class bitcell_base_array(design.design):
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width=self.width,
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height=wl_pin.height())
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# For every second row and column, add a via for gnd and vdd
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# For non-square via stacks, vertical/horizontal direction refers to the stack orientation in 2d space
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# Default uses prefered directions for each layer; this cell property is only currently used by s8 tech (03/20)
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try:
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force_power_pins_vertical = cell_properties.bitcell_force_power_pins_vertical
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except AttributeError:
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force_power_pins_vertical = None
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# Add vdd/gnd via stacks
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for row in range(self.row_size):
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for col in range(self.column_size):
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inst = self.cell_inst[row,col]
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for pin_name in ["vdd", "gnd"]:
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for pin in inst.get_pins(pin_name):
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self.add_power_pin(name=pin_name, loc=pin.center(), vertical=True, start_layer=pin.layer)
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self.add_power_pin(name=pin_name, loc=pin.center(), vertical=force_power_pins_vertical, start_layer=pin.layer)
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def _adjust_x_offset(self, xoffset, col, col_offset):
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tempx = xoffset
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