mirror of https://github.com/VLSIDA/OpenRAM.git
Fix delay numbers in hspice delay unit test.
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@ -62,16 +62,16 @@ class timing_sram_test(openram_test):
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'write0_power': [0.0494321],
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'write0_power': [0.0494321],
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'write1_power': [0.0457268]}
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'write1_power': [0.0457268]}
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elif OPTS.tech_name == "scn3me_subm":
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elif OPTS.tech_name == "scn3me_subm":
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golden_data = {'delay_hl': [6.473300000000001],
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golden_data = {'delay_hl': [6.0052],
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'delay_lh': [1.0442000000000002],
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'delay_lh': [2.2886],
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'leakage_power': 0.025569099999999997,
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'leakage_power': 0.025629199999999998,
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'min_period': 9.375,
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'min_period': 9.375,
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'read0_power': [8.0248],
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'read0_power': [8.8721],
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'read1_power': [7.5243],
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'read1_power': [8.3179],
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'slew_hl': [6.266000000000001],
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'slew_hl': [1.0746],
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'slew_lh': [0.7857840999999999],
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'slew_lh': [0.413426],
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'write0_power': [7.7587],
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'write0_power': [8.6601],
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'write1_power': [8.0425]}
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'write1_power': [8.0397]}
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else:
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else:
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self.assertTrue(False) # other techs fail
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self.assertTrue(False) # other techs fail
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# Check if no too many or too few results
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# Check if no too many or too few results
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