luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Zjog the WL enable. Min driver is 1.

This commit is contained in:
mrg 2020-09-28 12:24:55 -07:00
parent 6f06bb9dd5
commit d65eb16513
3 changed files with 11 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
compiler/modules/port_address.py
View File

@ -116,15 +116,13 @@ class port_address(design.design):
rbl_in_pin = self.rbl_driver_inst.get_pin("A") rbl_in_pin = self.rbl_driver_inst.get_pin("A")
rbl_in_pos = rbl_in_pin.center() rbl_in_pos = rbl_in_pin.center()
mid_pos = vector(en_pin.cx(), rbl_in_pin.cy())
self.add_via_stack_center(from_layer=rbl_in_pin.layer, self.add_via_stack_center(from_layer=rbl_in_pin.layer,
to_layer=en_pin.layer, to_layer=en_pin.layer,
offset=rbl_in_pos) offset=rbl_in_pos)
self.add_path(en_pin.layer, [rbl_in_pos, mid_pos, en_pos]) self.add_zjog(en_pin.layer, rbl_in_pos, en_pos)
self.add_layout_pin_segment_center(text="wl_en", self.add_layout_pin_rect_center(text="wl_en",
layer=en_pin.layer, layer=en_pin.layer,
start=mid_pos, offset=rbl_in_pos)
end=en_pos)
def add_modules(self): def add_modules(self):
@ -139,11 +137,11 @@ class port_address(design.design):
try: try:
local_array_size = OPTS.local_array_size local_array_size = OPTS.local_array_size
driver_size = int(self.num_cols / local_array_size) driver_size = max(int(self.num_cols / local_array_size), 1)
except AttributeError: except AttributeError:
local_array_size = 0 local_array_size = 0
# Defautl to FO4 # Defautl to FO4
driver_size = int(self.num_cols / 4) driver_size = max(int(self.num_cols / 4), 1)
# The polarity must be switched if we have a hierarchical wordline # The polarity must be switched if we have a hierarchical wordline
# to compensate for the local array inverters # to compensate for the local array inverters

3
compiler/options.py
View File

@ -30,6 +30,9 @@ class options(optparse.Values):
num_r_ports = 0 num_r_ports = 0
num_w_ports = 0 num_w_ports = 0
# By default, use local arrays with a max fanout of 16
#local_array_size = 16
# Write mask size, default will be overwritten with word_size if not user specified # Write mask size, default will be overwritten with word_size if not user specified
write_size = None write_size = None

4
compiler/pgates/wordline_driver.py
View File

@ -45,11 +45,11 @@ class wordline_driver(design.design):
try: try:
local_array_size = OPTS.local_array_size local_array_size = OPTS.local_array_size
driver_size = int(self.cols / local_array_size) driver_size = max(int(self.cols / local_array_size), 1)
except AttributeError: except AttributeError:
local_array_size = 0 local_array_size = 0
# Defautl to FO4 # Defautl to FO4
driver_size = int(self.cols / 4) driver_size = max(int(self.cols / 4), 1)
# The polarity must be switched if we have a hierarchical wordline # The polarity must be switched if we have a hierarchical wordline
# to compensate for the local array inverters # to compensate for the local array inverters