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Reimplement trim options (except on unit tests).

Browse Source 
Allow trim netlist to be used for delay and functional simulation.
Each class implements a "trim_insts" set of instances that can be removed.
By default far left, right, top and bottom cells in the bitcell arrays are kept.

Use lvs option in sp_write

Fix lvs option in sram.
This commit is contained in:
mrg
2021-04-07 16:07:56 -07:00
parent 31d3e6cb26
commit d609e4ea04
30 changed files with 147 additions and 206 deletions
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compiler/tests/21_hspice_delay_test.py
+29 -34
View File
@@ -30,19 +30,13 @@ class timing_sram_test(openram_test):
reload(characterizer)
from characterizer import delay
from sram_config import sram_config
c = sram_config(word_size=1,
c = sram_config(word_size=4,
num_words=16,
num_banks=1)
c.words_per_row=1
# c = sram_config(word_size=32,
# num_words=256,
# num_banks=1)
# c.words_per_row=2
c.recompute_sizes()
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = factory.create(module_type="sram", sram_config=c)
#import sys
#sys.exit(1)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
@@ -61,34 +55,35 @@ class timing_sram_test(openram_test):
data.update(port_data[0])
if OPTS.tech_name == "freepdk45":
golden_data = {'min_period': 0.898,
'write1_power': [0.2659137999999999],
'disabled_write0_power': [0.1782495],
'disabled_read0_power': [0.14490679999999997],
'write0_power': [0.3330119],
'disabled_write1_power': [0.1865223],
'leakage_power': 0.0014532,
'disabled_read1_power': [0.1627516],
'slew_lh': [0.25367799999999996],
'slew_hl': [0.25367799999999996],
'delay_lh': [0.23820930000000004],
'delay_hl': [0.23820930000000004],
'read1_power': [0.3005756],
'read0_power': [0.3005888]}
golden_data = {'delay_hl': [0.23941909999999997],
'delay_lh': [0.23941909999999997],
'disabled_read0_power': [0.18183159999999998],
'disabled_read1_power': [0.1979447],
'disabled_write0_power': [0.2129604],
'disabled_write1_power': [0.23266849999999997],
'leakage_power': 0.0019882,
'min_period': 0.938,
'read0_power': [0.4115467],
'read1_power': [0.41158859999999997],
'slew_hl': [0.2798571],
'slew_lh': [0.2798571],
'write0_power': [0.45873749999999996],
'write1_power': [0.40716199999999997]}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {'leakage_power': 0.0006356576000000001,
'write1_power': [11.292700000000002],
'read0_power': [12.98],
'disabled_write1_power': [8.3707],
'write0_power': [14.4447], 'delay_hl': [1.7445000000000002],
'disabled_read0_power': [6.4325],
'slew_hl': [1.7437],
'disabled_write0_power': [8.1307],
'slew_lh': [1.7437],
'read1_power': [12.9869],
'disabled_read1_power': [7.706],
'min_period': 6.25,
'delay_lh': [1.7445000000000002]}
golden_data = {'delay_hl': [1.7652000000000003],
'delay_lh': [1.7652000000000003],
'disabled_read0_power': [8.2716],
'disabled_read1_power': [9.5857],
'disabled_write0_power': [9.9825],
'disabled_write1_power': [10.598400000000002],
'leakage_power': 0.0006681718,
'min_period': 6.562,
'read0_power': [18.6446],
'read1_power': [18.5126],
'slew_hl': [1.9026],
'slew_lh': [1.9026],
'write0_power': [21.022600000000004],
'write1_power': [16.6377]}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
compiler/tests/21_ngspice_delay_test.py
+29 -29
View File
@@ -30,7 +30,7 @@ class timing_sram_test(openram_test):
reload(characterizer)
from characterizer import delay
from sram_config import sram_config
c = sram_config(word_size=1,
c = sram_config(word_size=4,
num_words=16,
num_banks=1)
c.words_per_row=1
@@ -55,35 +55,35 @@ class timing_sram_test(openram_test):
data.update(port_data[0])
if OPTS.tech_name == "freepdk45":
golden_data = {'slew_lh': [0.2592187],
'slew_hl': [0.2592187],
'delay_lh': [0.2465583],
'disabled_write0_power': [0.1924678],
'disabled_read0_power': [0.152483],
'write0_power': [0.3409064],
'disabled_read1_power': [0.1737818],
'read0_power': [0.3096708],
'read1_power': [0.3107916],
'delay_hl': [0.2465583],
'write1_power': [0.26915849999999997],
'leakage_power': 0.002044307,
'min_period': 0.898,
'disabled_write1_power': [0.201411]}
golden_data = {'delay_hl': [0.24671600000000002],
'delay_lh': [0.24671600000000002],
'disabled_read0_power': [0.1749204],
'disabled_read1_power': [0.1873704],
'disabled_write0_power': [0.204619],
'disabled_write1_power': [0.2262653],
'leakage_power': 0.0021375310000000002,
'min_period': 0.977,
'read0_power': [0.3856875],
'read1_power': [0.38856060000000003],
'slew_hl': [0.2842019],
'slew_lh': [0.2842019],
'write0_power': [0.45274410000000004],
'write1_power': [0.38727789999999995]}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {'delay_hl': [1.8435739999999998],
'delay_lh': [1.8435739999999998],
'disabled_read0_power': [5.917947],
'disabled_read1_power': [7.154297],
'disabled_write0_power': [7.696351],
'disabled_write1_power': [7.999409000000001],
'leakage_power': 0.004809726,
'min_period': 6.875,
'read0_power': [11.833079999999999],
'read1_power': [11.99236],
'slew_hl': [1.8668490000000002],
'slew_lh': [1.8668490000000002],
'write0_power': [13.287510000000001],
'write1_power': [10.416369999999999]}
golden_data = {'delay_hl': [1.882508],
'delay_lh': [1.882508],
'disabled_read0_power': [7.487227],
'disabled_read1_power': [8.749013],
'disabled_write0_power': [9.268901],
'disabled_write1_power': [9.962973],
'leakage_power': 0.0046686359999999994,
'min_period': 7.188,
'read0_power': [16.64011],
'read1_power': [17.20825],
'slew_hl': [2.039655],
'slew_lh': [2.039655],
'write0_power': [19.31883],
'write1_power': [15.297369999999999]}
else:
self.assertTrue(False) # other techs fail
compiler/tests/22_psram_1bank_2mux_func_test.py
+1 -5
View File
@@ -23,7 +23,6 @@ class psram_1bank_2mux_func_test(openram_test):
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
@@ -53,10 +52,7 @@ class psram_1bank_2mux_func_test(openram_test):
c.words_per_row,
c.num_banks))
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "sram.sp"
s.sp_write(tempspice)
f = functional(s.s, tempspice)
f = functional(s.s)
(fail, error) = f.run()
self.assertTrue(fail, error)
compiler/tests/22_psram_1bank_4mux_func_test.py
+1 -5
View File
@@ -24,7 +24,6 @@ class psram_1bank_4mux_func_test(openram_test):
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
@@ -54,11 +53,8 @@ class psram_1bank_4mux_func_test(openram_test):
c.words_per_row,
c.num_banks))
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "sram.sp"
s.sp_write(tempspice)
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
f = functional(s.s, tempspice, corner)
f = functional(s.s, corner=corner)
(fail, error) = f.run()
self.assertTrue(fail, error)
compiler/tests/22_psram_1bank_8mux_func_test.py
+1 -5
View File
@@ -24,7 +24,6 @@ class psram_1bank_8mux_func_test(openram_test):
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
@@ -54,10 +53,7 @@ class psram_1bank_8mux_func_test(openram_test):
c.words_per_row,
c.num_banks))
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "sram.sp"
s.sp_write(tempspice)
f = functional(s.s, tempspice)
f = functional(s.s)
(fail, error) = f.run()
self.assertTrue(fail, error)
compiler/tests/22_psram_1bank_nomux_func_test.py
+1 -5
View File
@@ -23,7 +23,6 @@ class psram_1bank_nomux_func_test(openram_test):
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
@@ -53,10 +52,7 @@ class psram_1bank_nomux_func_test(openram_test):
c.words_per_row,
c.num_banks))
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "sram.sp"
s.sp_write(tempspice)
f = functional(s.s, tempspice)
f = functional(s.s)
(fail, error) = f.run()
self.assertTrue(fail, error)
compiler/tests/22_sram_1bank_2mux_func_test.py
+1 -5
View File
@@ -24,7 +24,6 @@ class sram_1bank_2mux_func_test(openram_test):
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
@@ -43,10 +42,7 @@ class sram_1bank_2mux_func_test(openram_test):
c.words_per_row,
c.num_banks))
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "sram.sp"
s.sp_write(tempspice)
f = functional(s.s, tempspice)
f = functional(s.s)
(fail, error) = f.run()
self.assertTrue(fail, error)
compiler/tests/22_sram_1bank_2mux_global_func_test.py
+1 -5
View File
@@ -24,7 +24,6 @@ class sram_1bank_2mux_func_test(openram_test):
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
@@ -44,10 +43,7 @@ class sram_1bank_2mux_func_test(openram_test):
c.words_per_row,
c.num_banks))
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "sram.sp"
s.sp_write(tempspice)
f = functional(s.s, tempspice)
f = functional(s.s)
(fail, error) = f.run()
self.assertTrue(fail, error)
compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py
+1 -5
View File
@@ -24,7 +24,6 @@ class sram_1bank_2mux_sparecols_func_test(openram_test):
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
@@ -45,10 +44,7 @@ class sram_1bank_2mux_sparecols_func_test(openram_test):
c.num_spare_cols,
c.num_banks))
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "sram.sp"
s.sp_write(tempspice)
f = functional(s.s, tempspice)
f = functional(s.s)
(fail, error) = f.run()
self.assertTrue(fail, error)
compiler/tests/22_sram_1bank_4mux_func_test.py
+1 -5
View File
@@ -24,7 +24,6 @@ class sram_1bank_4mux_func_test(openram_test):
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
@@ -43,10 +42,7 @@ class sram_1bank_4mux_func_test(openram_test):
c.words_per_row,
c.num_banks))
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "sram.sp"
s.sp_write(tempspice)
f = functional(s.s, tempspice)
f = functional(s.s)
(fail, error) = f.run()
self.assertTrue(fail, error)
compiler/tests/22_sram_1bank_8mux_func_test.py
+1 -5
View File
@@ -24,7 +24,6 @@ class sram_1bank_8mux_func_test(openram_test):
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
@@ -46,10 +45,7 @@ class sram_1bank_8mux_func_test(openram_test):
c.words_per_row,
c.num_banks))
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "sram.sp"
s.sp_write(tempspice)
f = functional(s.s, tempspice)
f = functional(s.s)
(fail, error) = f.run()
self.assertTrue(fail, error)
compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py
+1 -5
View File
@@ -23,7 +23,6 @@ class psram_1bank_nomux_func_test(openram_test):
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 1
@@ -46,10 +45,7 @@ class psram_1bank_nomux_func_test(openram_test):
c.words_per_row,
c.num_banks))
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "sram.sp"
s.sp_write(tempspice)
f = functional(s.s, tempspice)
f = functional(s.s)
(fail, error) = f.run()
self.assertTrue(fail, error)
compiler/tests/22_sram_1bank_nomux_func_test.py
+1 -4
View File
@@ -42,10 +42,7 @@ class sram_1bank_nomux_func_test(openram_test):
c.words_per_row,
c.num_banks))
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "sram.sp"
s.sp_write(tempspice)
f = functional(s.s, tempspice)
f = functional(s.s)
(fail, error) = f.run()
self.assertTrue(fail, error)
compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py
+1 -4
View File
@@ -43,10 +43,7 @@ class sram_1bank_nomux_sparecols_func_test(openram_test):
c.words_per_row,
c.num_banks))
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "sram.sp"
s.sp_write(tempspice)
f = functional(s.s, tempspice)
f = functional(s.s)
(fail, error) = f.run()
self.assertTrue(fail, error)
compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py
+1 -5
View File
@@ -23,7 +23,6 @@ class sram_wmask_1w_1r_func_test(openram_test):
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 1
@@ -49,10 +48,7 @@ class sram_wmask_1w_1r_func_test(openram_test):
c.write_size,
c.num_banks))
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "sram.sp"
s.sp_write(tempspice)
f = functional(s.s, tempspice)
f = functional(s.s)
(fail, error) = f.run()
self.assertTrue(fail, error)
compiler/tests/22_sram_wmask_func_test.py
+1 -5
View File
@@ -24,7 +24,6 @@ class sram_wmask_func_test(openram_test):
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
@@ -45,10 +44,7 @@ class sram_wmask_func_test(openram_test):
c.write_size,
c.num_banks))
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "sram.sp"
s.sp_write(tempspice)
f = functional(s.s, tempspice)
f = functional(s.s)
(fail, error) = f.run()
self.assertTrue(fail, error)
compiler/tests/23_lib_sram_test.py
-1
View File
@@ -21,7 +21,6 @@ class lib_test(openram_test):
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
compiler/tests/26_sram_pex_test.py
+1 -1
View File
@@ -45,7 +45,7 @@ class sram_pex_test(openram_test):
tempspice = self.run_pex(s)
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
f = functional(s.s, tempspice, corner)
f = functional(s.s, spfile=tempspice, corner=corner)
(fail, error) = f.run()
self.assertTrue(fail, error)
compiler/tests/50_riscv_func_test.py
+1 -5
View File
@@ -24,7 +24,6 @@ class riscv_func_test(openram_test):
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
OPTS.local_array_size = 16
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
@@ -49,11 +48,8 @@ class riscv_func_test(openram_test):
c.words_per_row,
c.num_banks))
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "sram.sp"
s.sp_write(tempspice)
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
f = functional(s.s, tempspice, corner)
f = functional(s.s, corner=corner)
(fail, error) = f.run()
self.assertTrue(fail, error)
compiler/tests/testutils.py
+1 -1
View File
@@ -63,7 +63,7 @@ class openram_test(unittest.TestCase):
tempspice = "{}.sp".format(a.name)
tempgds = "{}.gds".format(a.name)
a.lvs_write("{0}{1}".format(OPTS.openram_temp, tempspice))
a.sp_write("{0}{1}".format(OPTS.openram_temp, tempspice), lvs=True)
# cannot write gds in netlist_only mode
if not OPTS.netlist_only:
a.gds_write("{0}{1}".format(OPTS.openram_temp, tempgds))