Reimplement trim options (except on unit tests).

Allow trim netlist to be used for delay and functional simulation.
Each class implements a "trim_insts" set of instances that can be removed.
By default far left, right, top and bottom cells in the bitcell arrays are kept.

Use lvs option in sp_write

Fix lvs option in sram.

compiler/modules/bitcell_array.py

@@ -64,7 +64,11 @@ class bitcell_array(bitcell_base_array):
                 self.cell_inst[row, col]=self.add_inst(name=name,
                                                        mod=self.cell)
                 self.connect_inst(self.get_bitcell_pins(row, col))
-
+                
+                # If it is a "core" cell, it could be trimmed for sim time
+                if col>0 and col<self.column_size-1 and row>0 and row<self.row_size-1:
+                    self.trim_insts.add(name)
+                    
     def analytical_power(self, corner, load):
         """Power of Bitcell array and bitline in nW."""