Reimplement trim options (except on unit tests).

Allow trim netlist to be used for delay and functional simulation.
Each class implements a "trim_insts" set of instances that can be removed.
By default far left, right, top and bottom cells in the bitcell arrays are kept.

Use lvs option in sp_write

Fix lvs option in sram.

compiler/characterizer/simulation.py

@@ -27,7 +27,10 @@ class simulation():
             self.num_spare_cols = 0
         else:
             self.num_spare_cols = self.sram.num_spare_cols
-        self.sp_file = spfile
+        if not spfile:
+            self.sp_file = OPTS.openram_temp + "sram.sp"
+        else:
+            self.sp_file = spfile
 
         self.all_ports = self.sram.all_ports
         self.readwrite_ports = self.sram.readwrite_ports