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https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-08 04:11:47 +02:00
Reimplement trim options (except on unit tests).
Allow trim netlist to be used for delay and functional simulation. Each class implements a "trim_insts" set of instances that can be removed. By default far left, right, top and bottom cells in the bitcell arrays are kept. Use lvs option in sp_write Fix lvs option in sram.
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@@ -21,13 +21,17 @@ class functional(simulation):
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for successful SRAM operation.
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"""
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def __init__(self, sram, spfile, corner=None, cycles=15, period=None, output_path=None):
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def __init__(self, sram, spfile=None, corner=None, cycles=15, period=None, output_path=None):
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super().__init__(sram, spfile, corner)
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# Seed the characterizer with a constant seed for unit tests
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if OPTS.is_unit_test:
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random.seed(12345)
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if not spfile:
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# self.sp_file is assigned in base class
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sram.sp_write(self.sp_file, trim=OPTS.trim_netlist)
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if not corner:
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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@@ -46,7 +50,18 @@ class functional(simulation):
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if not self.num_spare_cols:
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self.num_spare_cols = 0
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if self.num_spare_cols > 0:
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debug.error("Functional simulation not debugged with spare columns.")
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# FIXME: we need to remember the correct value of the spare columns
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self.max_value = 2 ** (self.word_size + self.num_spare_cols) - 1
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# If trim is set, specify the valid addresses
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self.valid_addresses = set()
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self.max_address = 2**self.addr_size - 1 + (self.num_spare_rows * self.words_per_row)
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if OPTS.trim_netlist:
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for i in range(self.words_per_row):
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self.valid_addresses.add(i)
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self.valid_addresses.add(self.max_address - i)
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self.probe_address, self.probe_data = '0' * self.addr_size, 0
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self.set_corner(corner)
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self.set_spice_constants()
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@@ -300,21 +315,16 @@ class functional(simulation):
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def gen_data(self):
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""" Generates a random word to write. """
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if not self.num_spare_cols:
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random_value = random.randint(0, (2 ** self.word_size) - 1)
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else:
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random_value1 = random.randint(0, (2 ** self.word_size) - 1)
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random_value2 = random.randint(0, (2 ** self.num_spare_cols) - 1)
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random_value = random_value1 + random_value2
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random_value = random.randint(0, self.max_value)
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data_bits = self.convert_to_bin(random_value, False)
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return data_bits
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def gen_addr(self):
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""" Generates a random address value to write to. """
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if self.num_spare_rows==0:
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random_value = random.randint(0, (2 ** self.addr_size) - 1)
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if self.valid_addresses:
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random_value = random.sample(self.valid_addresses, 1)[0]
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else:
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random_value = random.randint(0, ((2 ** (self.addr_size - 1) - 1)) + (self.num_spare_rows * self.words_per_row))
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random_value = random.randint(0, self.max_address)
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addr_bits = self.convert_to_bin(random_value, True)
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return addr_bits
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