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Merge branch 'dev' into char

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Bugra Onal
2023-07-19 12:06:34 -07:00
parent 9fa25690ce 5dbc22091c
commit d53353b5be
91 changed files with 2445 additions and 546 deletions
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compiler/tests/14_capped_replica_bitcell_array_bothrbl_1rw_1r_test.py
+3 -8
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@@ -14,7 +14,7 @@ from openram.sram_factory import factory
from openram import OPTS
class capped_replica_bitcell_array_1rw_1r_test(openram_test):
class capped_replica_bitcell_array_bothrbl_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -25,13 +25,8 @@ class capped_replica_bitcell_array_1rw_1r_test(openram_test):
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 4x4 array left and right replica for dp cell")
a = factory.create(module_type="capped_replica_bitcell_array",
cols=4,
rows=4,
rbl=[1, 1],
left_rbl=[0],
right_rbl=[1])
debug.info(2, "Testing 4x4 capped replica array for 1rw1r cell with both replica columns")
a = factory.create(module_type="capped_replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1])
self.local_check(a)
openram.end_openram()
compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_1r_test.py
Executable
+40
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@@ -0,0 +1,40 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class capped_replica_bitcell_array_dummies_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 4x4 capped replica array for 1rw1r cell with dummy rows only")
a = factory.create(module_type="capped_replica_bitcell_array", cols=4, rows=4, rbl=[1, 1])
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py
Executable
+40
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@@ -0,0 +1,40 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class capped_replica_bitcell_array_dummies_1rw_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 7x5 capped replica array for 1rw cell with dummy row only")
a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0])
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py
+4 -7
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@@ -14,7 +14,7 @@ from openram.sram_factory import factory
from openram import OPTS
class capped_replica_bitcell_array_1rw_1r_test(openram_test):
class capped_replica_bitcell_array_leftrbl_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -25,16 +25,13 @@ class capped_replica_bitcell_array_1rw_1r_test(openram_test):
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 4x4 left replica array for dp cell")
a = factory.create(module_type="capped_replica_bitcell_array",
cols=4,
rows=4,
rbl=[1, 1],
left_rbl=[0])
debug.info(2, "Testing 4x4 capped replica array for 1rw1r cell with left replica column")
a = factory.create(module_type="capped_replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0])
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py
+3 -2
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@@ -14,7 +14,7 @@ from openram.sram_factory import factory
from openram import OPTS
class capped_replica_bitcell_array_test(openram_test):
class capped_replica_bitcell_array_leftrbl_1rw_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -23,8 +23,9 @@ class capped_replica_bitcell_array_test(openram_test):
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 4x4 array for bitcell")
debug.info(2, "Testing 7x5 capped replica array for 1rw cell with left replica column")
a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0])
self.local_check(a)
compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_1r_test.py
+3 -6
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@@ -14,7 +14,7 @@ from openram.sram_factory import factory
from openram import OPTS
class capped_replica_bitcell_array_1rw_1r_test(openram_test):
class capped_replica_bitcell_array_norbl_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -25,11 +25,8 @@ class capped_replica_bitcell_array_1rw_1r_test(openram_test):
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 4x4 non-replica array for dp cell")
a = factory.create(module_type="capped_replica_bitcell_array",
cols=4,
rows=4,
rbl=[1, 1])
debug.info(2, "Testing 4x4 capped replica array for 1rw1r cell without replica columns or dummy rows")
a = factory.create(module_type="capped_replica_bitcell_array", cols=4, rows=4, rbl=[0, 0])
self.local_check(a)
openram.end_openram()
compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py
+4 -3
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@@ -14,7 +14,7 @@ from openram.sram_factory import factory
from openram import OPTS
class capped_replica_bitcell_array_test(openram_test):
class capped_replica_bitcell_array_norbl_1rw_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -23,9 +23,10 @@ class capped_replica_bitcell_array_test(openram_test):
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 4x4 array for bitcell")
a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0])
debug.info(2, "Testing 7x5 capped replica array for 1rw cell without replica column or dummy row")
a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[0, 0])
self.local_check(a)
openram.end_openram()
compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py
+4 -7
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@@ -14,7 +14,7 @@ from openram.sram_factory import factory
from openram import OPTS
class capped_replica_bitcell_array_1rw_1r_test(openram_test):
class capped_replica_bitcell_array_rightrbl_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -25,16 +25,13 @@ class capped_replica_bitcell_array_1rw_1r_test(openram_test):
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 4x4 left replica array for dp cell")
a = factory.create(module_type="capped_replica_bitcell_array",
cols=4,
rows=4,
rbl=[1, 1],
right_rbl=[1])
debug.info(2, "Testing 4x4 capped replica array for 1rw1r cell with right replica column")
a = factory.create(module_type="capped_replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1])
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py
+3 -8
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@@ -14,7 +14,7 @@ from openram.sram_factory import factory
from openram import OPTS
class replica_bitcell_array_1rw_1r_test(openram_test):
class replica_bitcell_array_bothrbl_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -25,13 +25,8 @@ class replica_bitcell_array_1rw_1r_test(openram_test):
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 4x4 array left and right replica for dp cell")
a = factory.create(module_type="replica_bitcell_array",
cols=4,
rows=4,
rbl=[1, 1],
left_rbl=[0],
right_rbl=[1])
debug.info(2, "Testing 4x4 replica array for 1rw1r cell with both replica columns")
a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1])
self.local_check(a)
openram.end_openram()
compiler/tests/14_replica_bitcell_array_dummies_1rw_1r_test.py
Executable
+40
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@@ -0,0 +1,40 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class replica_bitcell_array_dummies_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 4x4 replica array for 1rw1r cell with dummy rows only")
a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1])
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py
Executable
+40
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@@ -0,0 +1,40 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class replica_bitcell_array_dummies_1rw_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 7x5 replica array for 1rw cell with dummy row only")
a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0])
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py
+4 -7
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@@ -14,7 +14,7 @@ from openram.sram_factory import factory
from openram import OPTS
class replica_bitcell_array_1rw_1r_test(openram_test):
class replica_bitcell_array_leftrbl_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -25,16 +25,13 @@ class replica_bitcell_array_1rw_1r_test(openram_test):
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 4x4 left replica array for dp cell")
a = factory.create(module_type="replica_bitcell_array",
cols=4,
rows=4,
rbl=[1, 1],
left_rbl=[0])
debug.info(2, "Testing 4x4 replica array for 1rw1r cell with left replica column")
a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0])
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py
+3 -2
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@@ -14,7 +14,7 @@ from openram.sram_factory import factory
from openram import OPTS
class replica_bitcell_array_test(openram_test):
class replica_bitcell_array_leftrbl_1rw_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -23,8 +23,9 @@ class replica_bitcell_array_test(openram_test):
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 4x4 array for bitcell")
debug.info(2, "Testing 7x5 replica array for 1rw cell with left replica column")
a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0])
self.local_check(a)
compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py
+3 -6
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@@ -14,7 +14,7 @@ from openram.sram_factory import factory
from openram import OPTS
class replica_bitcell_array_1rw_1r_test(openram_test):
class replica_bitcell_array_norbl_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -25,11 +25,8 @@ class replica_bitcell_array_1rw_1r_test(openram_test):
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 4x4 non-replica array for dp cell")
a = factory.create(module_type="replica_bitcell_array",
cols=4,
rows=4,
rbl=[1, 1])
debug.info(2, "Testing 4x4 replica array for 1rw1r cell without replica columns or dummy rows")
a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[0, 0])
self.local_check(a)
openram.end_openram()
compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py
+4 -3
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@@ -14,7 +14,7 @@ from openram.sram_factory import factory
from openram import OPTS
class replica_bitcell_array_test(openram_test):
class replica_bitcell_array_norbl_1rw_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -23,9 +23,10 @@ class replica_bitcell_array_test(openram_test):
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 4x4 array for bitcell")
a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0])
debug.info(2, "Testing 7x5 replica array for 1rw cell without replica column or dummy row")
a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[0, 0])
self.local_check(a)
openram.end_openram()
compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py
+4 -7
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@@ -14,7 +14,7 @@ from openram.sram_factory import factory
from openram import OPTS
class replica_bitcell_array_1rw_1r_test(openram_test):
class replica_bitcell_array_rightrbl_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -25,16 +25,13 @@ class replica_bitcell_array_1rw_1r_test(openram_test):
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 4x4 left replica array for dp cell")
a = factory.create(module_type="replica_bitcell_array",
cols=4,
rows=4,
rbl=[1, 1],
right_rbl=[1])
debug.info(2, "Testing 4x4 replica array for 1rw1r cell with right replica column")
a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1])
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
compiler/tests/15_global_bitcell_array_norbl_1rw_1r_test.py
Executable
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@@ -0,0 +1,40 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class global_bitcell_array_norbl_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 2 x 4x4 global bitcell array for 1rw1r cell without replica columns")
a = factory.create(module_type="global_bitcell_array", cols=[4, 4, 4], rows=4, rbl=[0, 0], left_rbl=[], right_rbl=[])
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/15_global_bitcell_array_norbl_1rw_test.py
Executable
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@@ -0,0 +1,40 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class global_bitcell_array_norbl_1rw_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 2 x 4x4 global bitcell array for 1rw cell without replica column")
a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4, rbl=[0, 0], left_rbl=[])
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/15_global_bitcell_array_rbl_1rw_1r_test.py
Executable
+40
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@@ -0,0 +1,40 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class global_bitcell_array_rbl_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 2 x 4x4 global bitcell array for 1rw1r cell with replica columns")
a = factory.create(module_type="global_bitcell_array", cols=[4, 4, 4], rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1])
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/15_global_bitcell_array_rbl_1rw_test.py
Executable
+40
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@@ -0,0 +1,40 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class global_bitcell_array_rbl_1rw_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 2 x 4x4 global bitcell array for 1rw cell with left replica column")
a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4, rbl=[1, 0], left_rbl=[0])
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/15_local_bitcell_array_1rw_1r_test.py
-55
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@@ -1,55 +0,0 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
# @unittest.skip("SKIPPING 05_local_bitcell_array_test")
class local_bitcell_array_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r without replica")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1])
self.local_check(a)
debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with replica column")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1])
self.local_check(a)
debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with replica column")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0])
self.local_check(a)
debug.info(2, "Testing 4x4 local bitcell array for cell_1rw_1r with replica column")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1])
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/15_local_bitcell_array_bothrbl_1rw_1r_test.py
Executable
+40
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@@ -0,0 +1,40 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class local_bitcell_array_bothrbl_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 4x4 local bitcell array for 1rw1r cell with both replica columns")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1])
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/15_local_bitcell_array_dummies_1rw_1r_test.py
Executable
+40
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@@ -0,0 +1,40 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class local_bitcell_array_dummies_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 4x4 local bitcell array for 1rw1r cell with dummy rows only")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1])
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/15_local_bitcell_array_dummies_1rw_test.py
Executable
+40
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@@ -0,0 +1,40 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class local_bitcell_array_dummies_1rw_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 7x5 local bitcell array for 1rw cell with dummy row only")
a = factory.create(module_type="local_bitcell_array", cols=7, rows=5, rbl=[1, 0])
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/15_local_bitcell_array_leftrbl_1rw_1r_test.py
Executable
+40
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@@ -0,0 +1,40 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class local_bitcell_array_leftrbl_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 4x4 local bitcell array for 1rw1r cell with left replica column")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0])
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/15_local_bitcell_array_leftrbl_1rw_test.py
Executable
+40
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@@ -0,0 +1,40 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class local_bitcell_array_leftrbl_1rw_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 7x5 local bitcell array for 1rw cell with left replica column")
a = factory.create(module_type="local_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0])
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/15_local_bitcell_array_norbl_1rw_1r_test.py
Executable
+40
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@@ -0,0 +1,40 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class local_bitcell_array_norbl_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 4x4 local bitcell array for 1rw1r cell without replica columns or dummy rows")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[0, 0])
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/15_local_bitcell_array_norbl_1rw_test.py
Executable
+40
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@@ -0,0 +1,40 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class local_bitcell_array_norbl_1rw_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 7x5 local bitcell array for 1rw cell without replica column or dummy row")
a = factory.create(module_type="local_bitcell_array", cols=7, rows=5, rbl=[0, 0])
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/15_local_bitcell_array_rightrbl_1rw_1r_test.py
Executable
+40
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@@ -0,0 +1,40 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class local_bitcell_array_rightrbl_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 4x4 local bitcell array for 1rw1r cell with right replica column")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1])
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/16_control_logic_delay_multiport_test.py
Executable
+60
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@@ -0,0 +1,60 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
"""
Run a regression test on a control_logic_delay
"""
import sys, os
import unittest
from testutils import header,openram_test
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class control_logic_delay_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
# check control logic for multi-port
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell = "replica_pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 1
OPTS.num_r_ports = 1
debug.info(1, "Testing sample for control_logic_delay for multiport, combined read-write control logic")
a = factory.create(module_type="control_logic_delay", num_rows=128, words_per_row=1, word_size=8, port_type="rw")
self.local_check(a)
# OPTS.num_rw_ports = 0
# OPTS.num_w_ports = 1
debug.info(1, "Testing sample for control_logic_delay for multiport, only write control logic")
a = factory.create(module_type="control_logic_delay", num_rows=128, words_per_row=1, word_size=8, port_type="w")
self.local_check(a)
# OPTS.num_w_ports = 0
# OPTS.num_r_ports = 1
debug.info(1, "Testing sample for control_logic_delay for multiport, only read control logic")
a = factory.create(module_type="control_logic_delay", num_rows=128, words_per_row=1, word_size=8, port_type="r")
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()
compiler/tests/15_global_bitcell_array_test.py → compiler/tests/16_control_logic_delay_r_test.py
+4 -10
View File
@@ -11,29 +11,23 @@ import unittest
from testutils import *
import openram
from openram.sram_factory import factory
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
# @unittest.skip("SKIPPING 05_global_bitcell_array_test")
class global_bitcell_array_test(openram_test):
class control_logic_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
# debug.info(2, "Testing 2 x 4x4 global bitcell array for 6t_cell")
# a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4)
# self.local_check(a)
debug.info(2, "Testing 2 x 4x4 global bitcell array for 6t_cell")
a = factory.create(module_type="global_bitcell_array", cols=[10, 6], rows=4)
debug.info(1, "Testing sample for control_logic_r")
a = factory.create(module_type="control_logic_delay", num_rows=128, words_per_row=1, word_size=32, port_type="r")
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
compiler/tests/15_local_bitcell_array_test.py → compiler/tests/16_control_logic_delay_rw_test.py
+3 -9
View File
@@ -16,24 +16,18 @@ from openram.sram_factory import factory
from openram import OPTS
# @unittest.skip("SKIPPING 05_local_bitcell_array_test")
class local_bitcell_array_test(openram_test):
class control_logic_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
debug.info(2, "Testing 4x4 local bitcell array for 6t_cell without replica")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0])
self.local_check(a)
debug.info(2, "Testing 4x4 local bitcell array for 6t_cell with replica column")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0], left_rbl=[0])
debug.info(1, "Testing sample for control_logic_rw")
a = factory.create(module_type="control_logic_delay", num_rows=128, words_per_row=1, word_size=32)
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
compiler/tests/16_control_logic_delay_w_test.py
Executable
+36
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@@ -0,0 +1,36 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class control_logic_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
debug.info(1, "Testing sample for control_logic_w")
a = factory.create(module_type="control_logic_delay", num_rows=128, words_per_row=1, word_size=32, port_type="w")
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/16_control_logic_multiport_test.py
+1 -1
View File
@@ -33,7 +33,7 @@ class control_logic_test(openram_test):
OPTS.num_w_ports = 1
OPTS.num_r_ports = 1
debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
debug.info(1, "Testing sample for control_logic for multiport, combined read-write control logic")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="rw")
self.local_check(a)
compiler/tests/18_port_address_16rows_1rw_1r_test.py
+1 -1
View File
@@ -27,7 +27,7 @@ class port_address_1rw_1r_test(openram_test):
openram.setup_bitcell()
debug.info(1, "Port address 16 rows")
a = factory.create("port_address", cols=16, rows=16, port=0)
a = factory.create("port_address", cols=16, rows=16, port=0, has_rbl=True)
self.local_check(a)
openram.end_openram()
compiler/tests/18_port_address_16rows_test.py
+1 -1
View File
@@ -21,7 +21,7 @@ class port_address_test(openram_test):
openram.init_openram(config_file, is_unit_test=True)
debug.info(1, "Port address 16 rows")
a = factory.create("port_address", cols=16, rows=16, port=0)
a = factory.create("port_address", cols=16, rows=16, port=0, has_rbl=True)
self.local_check(a)
openram.end_openram()
compiler/tests/18_port_address_256rows_1rw_1r_test.py
+1 -1
View File
@@ -27,7 +27,7 @@ class port_address_1rw_1r_test(openram_test):
openram.setup_bitcell()
debug.info(1, "Port address 256 rows")
a = factory.create("port_address", cols=256, rows=256, port=1)
a = factory.create("port_address", cols=256, rows=256, port=1, has_rbl=True)
self.local_check(a)
openram.end_openram()
compiler/tests/18_port_address_512rows_test.py
+1 -1
View File
@@ -21,7 +21,7 @@ class port_address_test(openram_test):
openram.init_openram(config_file, is_unit_test=True)
debug.info(1, "Port address 512 rows")
a = factory.create("port_address", cols=256, rows=512, port=0)
a = factory.create("port_address", cols=256, rows=512, port=0, has_rbl=True)
self.local_check(a)
openram.end_openram()
compiler/tests/18_port_data_16mux_1rw_1r_test.py
+2 -2
View File
@@ -34,9 +34,9 @@ class port_data_1rw_1r_test(openram_test):
c.words_per_row=16
c.recompute_sizes()
debug.info(1, "Sixteen way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
a = factory.create("port_data", sram_config=c, port=1)
a = factory.create("port_data", sram_config=c, port=1, has_rbl=True)
self.local_check(a)
openram.end_openram()
compiler/tests/18_port_data_16mux_test.py
+1 -1
View File
@@ -38,7 +38,7 @@ class port_data_test(openram_test):
c.words_per_row=16
c.recompute_sizes()
debug.info(1, "Sixteen way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
openram.end_openram()
compiler/tests/18_port_data_2mux_1rw_1r_test.py
+2 -2
View File
@@ -33,9 +33,9 @@ class port_data_1rw_1r_test(openram_test):
c.words_per_row=2
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
a = factory.create("port_data", sram_config=c, port=1)
a = factory.create("port_data", sram_config=c, port=1, has_rbl=True)
self.local_check(a)
openram.end_openram()
compiler/tests/18_port_data_2mux_test.py
+1 -1
View File
@@ -37,7 +37,7 @@ class port_data_test(openram_test):
c.words_per_row=2
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
openram.end_openram()
compiler/tests/18_port_data_4mux_1rw_1r_test.py
+2 -2
View File
@@ -33,9 +33,9 @@ class port_data_1rw_1r_test(openram_test):
c.words_per_row=4
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
a = factory.create("port_data", sram_config=c, port=1)
a = factory.create("port_data", sram_config=c, port=1, has_rbl=True)
self.local_check(a)
openram.end_openram()
compiler/tests/18_port_data_4mux_test.py
+1 -1
View File
@@ -37,7 +37,7 @@ class port_data_test(openram_test):
c.words_per_row=4
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
openram.end_openram()
compiler/tests/18_port_data_8mux_1rw_1r_test.py
+2 -2
View File
@@ -34,9 +34,9 @@ class port_data_1rw_1r_test(openram_test):
c.words_per_row=8
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
a = factory.create("port_data", sram_config=c, port=1)
a = factory.create("port_data", sram_config=c, port=1, has_rbl=True)
self.local_check(a)
openram.end_openram()
compiler/tests/18_port_data_8mux_test.py
+1 -1
View File
@@ -38,7 +38,7 @@ class port_data_test(openram_test):
c.words_per_row=8
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
openram.end_openram()
compiler/tests/18_port_data_nomux_1rw_1r_test.py
+2 -2
View File
@@ -32,9 +32,9 @@ class port_data_1rw_1r_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
a = factory.create("port_data", sram_config=c, port=1)
a = factory.create("port_data", sram_config=c, port=1, has_rbl=True)
self.local_check(a)
openram.end_openram()
compiler/tests/18_port_data_nomux_test.py
+1 -1
View File
@@ -36,7 +36,7 @@ class port_data_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
openram.end_openram()
compiler/tests/18_port_data_spare_cols_test.py
+12 -12
View File
@@ -28,14 +28,14 @@ class port_data_spare_cols_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
c.num_words=32
c.words_per_row=2
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
c.num_words=64
@@ -43,7 +43,7 @@ class port_data_spare_cols_test(openram_test):
c.num_spare_cols=3
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
c.word_size=2
@@ -52,7 +52,7 @@ class port_data_spare_cols_test(openram_test):
c.num_spare_cols=4
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
OPTS.num_rw_ports = 0
@@ -64,27 +64,27 @@ class port_data_spare_cols_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
a = factory.create("port_data", sram_config=c, port=1)
a = factory.create("port_data", sram_config=c, port=1, has_rbl=True)
self.local_check(a)
c.num_words=32
c.words_per_row=2
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
a = factory.create("port_data", sram_config=c, port=1)
a = factory.create("port_data", sram_config=c, port=1, has_rbl=True)
self.local_check(a)
c.num_words=64
c.words_per_row=4
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
a = factory.create("port_data", sram_config=c, port=1)
a = factory.create("port_data", sram_config=c, port=1, has_rbl=True)
self.local_check(a)
c.word_size=2
@@ -92,9 +92,9 @@ class port_data_spare_cols_test(openram_test):
c.words_per_row=8
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
a = factory.create("port_data", sram_config=c, port=1)
a = factory.create("port_data", sram_config=c, port=1, has_rbl=True)
self.local_check(a)
openram.end_openram()
compiler/tests/18_port_data_wmask_1rw_1r_test.py
+12 -12
View File
@@ -33,28 +33,28 @@ class port_data_wmask_1rw_1r_test(openram_test):
c.words_per_row = 1
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
c.num_words = 32
c.words_per_row = 2
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
c.num_words = 64
c.words_per_row = 4
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
c.num_words = 128
c.words_per_row = 8
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
OPTS.num_rw_ports = 0
@@ -66,27 +66,27 @@ class port_data_wmask_1rw_1r_test(openram_test):
c.words_per_row = 1
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
a = factory.create("port_data", sram_config=c, port=1)
a = factory.create("port_data", sram_config=c, port=1, has_rbl=True)
self.local_check(a)
#
c.num_words = 32
c.words_per_row = 2
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
a = factory.create("port_data", sram_config=c, port=1)
a = factory.create("port_data", sram_config=c, port=1, has_rbl=True)
self.local_check(a)
c.num_words = 64
c.words_per_row = 4
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
a = factory.create("port_data", sram_config=c, port=1)
a = factory.create("port_data", sram_config=c, port=1, has_rbl=True)
self.local_check(a)
c.word_size = 8
@@ -94,9 +94,9 @@ class port_data_wmask_1rw_1r_test(openram_test):
c.words_per_row = 8
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
a = factory.create("port_data", sram_config=c, port=1)
a = factory.create("port_data", sram_config=c, port=1, has_rbl=True)
self.local_check(a)
openram.end_openram()
compiler/tests/18_port_data_wmask_test.py
+12 -12
View File
@@ -37,28 +37,28 @@ class port_data_wmask_test(openram_test):
c.words_per_row = 1
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
c.num_words = 32
c.words_per_row = 2
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
c.num_words = 64
c.words_per_row = 4
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
c.num_words = 128
c.words_per_row = 8
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
OPTS.num_rw_ports = 0
@@ -70,27 +70,27 @@ class port_data_wmask_test(openram_test):
c.words_per_row = 1
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
a = factory.create("port_data", sram_config=c, port=1)
a = factory.create("port_data", sram_config=c, port=1, has_rbl=True)
self.local_check(a)
#
c.num_words = 32
c.words_per_row = 2
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
a = factory.create("port_data", sram_config=c, port=1)
a = factory.create("port_data", sram_config=c, port=1, has_rbl=True)
self.local_check(a)
c.num_words = 64
c.words_per_row = 4
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
a = factory.create("port_data", sram_config=c, port=1)
a = factory.create("port_data", sram_config=c, port=1, has_rbl=True)
self.local_check(a)
c.word_size = 8
@@ -98,9 +98,9 @@ class port_data_wmask_test(openram_test):
c.words_per_row = 8
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("port_data", sram_config=c, port=0)
a = factory.create("port_data", sram_config=c, port=0, has_rbl=True)
self.local_check(a)
a = factory.create("port_data", sram_config=c, port=1)
a = factory.create("port_data", sram_config=c, port=1, has_rbl=True)
self.local_check(a)
openram.end_openram()
compiler/tests/15_global_bitcell_array_1rw_1r_test.py → compiler/tests/19_single_bank_nomux_norbl_1rw_1r_test.py
+10 -8
View File
@@ -16,25 +16,27 @@ from openram.sram_factory import factory
from openram import OPTS
# @unittest.skip("SKIPPING 05_global_bitcell_array_test")
class global_bitcell_array_test(openram_test):
class single_bank_nomux_norbl_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
from openram import sram_config
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 2 x 4x4 global bitcell array for cell_1rw_1r")
a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4)
self.local_check(a)
c = sram_config(word_size=4,
num_words=16)
# debug.info(2, "Testing 4x4 local bitcell array for 6t_cell with replica column")
# a = factory.create(module_type="local_bitcell_array", cols=4, left_rbl=1, rows=4, ports=[0])
# self.local_check(a)
c.words_per_row=1
OPTS.control_logic = "control_logic_delay"
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
openram.end_openram()
compiler/tests/19_single_bank_nomux_norbl_test.py
Executable
+54
View File
@@ -0,0 +1,54 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class single_bank_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
from openram import sram_config
if OPTS.tech_name == "sky130":
num_spare_rows = 1
num_spare_cols = 1
else:
num_spare_rows = 0
num_spare_cols = 0
c = sram_config(word_size=4,
num_words=16,
num_spare_cols=num_spare_cols,
num_spare_rows=num_spare_rows)
c.words_per_row=1
OPTS.control_logic = "control_logic_delay"
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("bank", sram_config=c)
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/20_sram_1bank_nomux_norbl_1rw_1r_test.py
Executable
+58
View File
@@ -0,0 +1,58 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class sram_1bank_nomux_norbl_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
from openram import sram_config
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
openram.setup_bitcell()
c = sram_config(word_size=4,
num_words=16,
num_banks=1)
c.words_per_row=1
OPTS.control_logic = "control_logic_delay"
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w sram "
"with {} bit words, {} words, {} words per "
"row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/20_sram_1bank_nomux_norbl_test.py
Executable
+58
View File
@@ -0,0 +1,58 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
class sram_1bank_nomux_norbl_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
from openram import sram_config
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
openram.setup_bitcell()
c = sram_config(word_size=4,
num_words=16,
num_banks=1)
c.words_per_row=1
OPTS.control_logic = "control_logic_delay"
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w sram "
"with {} bit words, {} words, {} words per "
"row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())
compiler/tests/Makefile
+69 -50
View File
@@ -32,6 +32,7 @@ BROKEN_STAMPS = \
%/20_psram_1bank_2mux_test.ok \
%/21_hspice_delay_test.ok \
%/21_hspice_setuphold_test.ok \
%/21_xyce_delay_test.ok \
%/22_psram_1bank_2mux_func_test.ok \
%/22_psram_1bank_4mux_func_test.ok \
%/22_psram_1bank_8mux_func_test.ok \
@@ -69,8 +70,11 @@ BROKEN_STAMPS = \
freepdk45/10_rom_wordline_driver_array_test.ok \
freepdk45/14_rom_array_test.ok \
freepdk45/16_rom_control_logic_test.ok \
freepdk45/16_control_logic_delay_multiport_test.ok \
freepdk45/16_control_logic_delay_rw_test.ok \
freepdk45/16_control_logic_delay_r_test.ok \
freepdk45/16_control_logic_delay_w_test.ok \
freepdk45/19_rom_bank_test.ok \
freepdk45/21_xyce_delay_test.ok \
scn4m_subm/06_rom_decoder_test.ok \
scn4m_subm/07_rom_column_mux_array_test.ok \
scn4m_subm/08_rom_decoder_buffer_array_test.ok \
@@ -80,8 +84,8 @@ BROKEN_STAMPS = \
scn4m_subm/16_rom_control_logic_test.ok \
scn4m_subm/19_rom_bank_test.ok \
scn4m_subm/19_single_bank_global_bitline_test.ok \
scn4m_subm/21_xyce_delay_test.ok \
sky130/01_library_test.ok \
sky130/03_wire_test.ok \
sky130/04_column_mux_pbitcell_test.ok \
sky130/04_dummy_pbitcell_test.ok \
sky130/04_pbitcell_test.ok \
@@ -89,15 +93,78 @@ BROKEN_STAMPS = \
sky130/04_pand4_test.ok \
sky130/04_precharge_pbitcell_test.ok \
sky130/04_replica_pbitcell_test.ok \
sky130/04_dummy_pbitcell_1rw1r1w_test.ok \
sky130/04_dummy_pbitcell_1rw_test.ok \
sky130/04_replica_pbitcell_1rw1r1w_test.ok \
sky130/04_replica_pbitcell_1rw_test.ok \
sky130/05_pbitcell_array_test.ok \
sky130/05_bitcell_array_test.ok \
sky130/05_bitcell_array_1rw_1r_test.ok \
sky130/05_dummy_array_test.ok \
sky130/06_hierarchical_decoder_132row_test.ok \
sky130/06_hierarchical_decoder_512row_test.ok \
sky130/06_hierarchical_decoder_64row_test.ok \
sky130/06_hierarchical_decoder_pbitcell_test.ok \
sky130/07_column_mux_array_pbitcell_test.ok \
sky130/10_write_driver_array_spare_cols_test.ok \
sky130/10_write_driver_array_wmask_spare_cols_test.ok \
sky130/14_capped_replica_bitcell_array_dummies_1rw_test.ok \
sky130/14_capped_replica_bitcell_array_leftrbl_1rw_test.ok \
sky130/14_capped_replica_bitcell_array_norbl_1rw_1r_test.ok \
sky130/14_capped_replica_bitcell_array_norbl_1rw_test.ok \
sky130/14_replica_bitcell_array_dummies_1rw_test.ok \
sky130/14_replica_bitcell_array_leftrbl_1rw_test.ok \
sky130/14_replica_bitcell_array_norbl_1rw_1r_test.ok \
sky130/14_replica_bitcell_array_norbl_1rw_test.ok \
sky130/14_replica_column_1rw_1r_test.ok \
sky130/14_replica_column_1rw_test.ok \
sky130/14_replica_pbitcell_1rw1r_array_test.ok \
sky130/14_replica_pbitcell_1rw_array_test.ok \
sky130/15_global_bitcell_array_norbl_1rw_1r_test.ok \
sky130/15_global_bitcell_array_norbl_1rw_test.ok \
sky130/15_global_bitcell_array_rbl_1rw_1r_test.ok \
sky130/15_global_bitcell_array_rbl_1rw_test.ok \
sky130/15_local_bitcell_array_dummies_1rw_test.ok \
sky130/15_local_bitcell_array_leftrbl_1rw_test.ok \
sky130/15_local_bitcell_array_norbl_1rw_1r_test.ok \
sky130/15_local_bitcell_array_norbl_1rw_test.ok \
sky130/16_control_logic_delay_multiport_test.ok \
sky130/16_control_logic_delay_rw_test.ok \
sky130/16_control_logic_delay_r_test.ok \
sky130/16_control_logic_delay_w_test.ok \
sky130/18_port_address_512rows_test.ok \
sky130/18_port_data_spare_cols_test.ok \
sky130/19_single_bank_2mux_test.ok \
sky130/19_single_bank_4mux_test.ok \
sky130/19_single_bank_8mux_test.ok \
sky130/19_single_bank_global_bitline_test.ok \
sky130/19_single_bank_nomux_test.ok \
sky130/19_single_bank_nomux_norbl_1rw_1r_test.ok \
sky130/19_single_bank_nomux_norbl_test.ok \
sky130/19_single_bank_spare_cols_test.ok \
sky130/19_single_bank_wmask_test.ok \
sky130/19_pmulti_bank_test.ok \
sky130/19_psingle_bank_test.ok \
sky130/19_bank_select_pbitcell_test.ok \
sky130/20_psram_1bank_4mux_1rw_1r_test.ok \
sky130/20_sram_1bank_2mux_1rw_1r_spare_cols_test.ok \
sky130/20_sram_1bank_2mux_1w_1r_spare_cols_test.ok \
sky130/20_sram_1bank_2mux_global_test.ok \
sky130/20_sram_1bank_2mux_test.ok \
sky130/20_sram_1bank_2mux_wmask_spare_cols_test.ok \
sky130/20_sram_1bank_2mux_wmask_test.ok \
sky130/20_sram_1bank_4mux_test.ok \
sky130/20_sram_1bank_8mux_test.ok \
sky130/20_sram_1bank_nomux_norbl_1rw_1r_test.ok \
sky130/20_sram_1bank_nomux_norbl_test.ok \
sky130/20_sram_1bank_nomux_spare_cols_test.ok \
sky130/20_sram_1bank_nomux_test.ok \
sky130/20_sram_1bank_nomux_wmask_test.ok \
sky130/20_sram_1bank_ring_test.ok \
sky130/21_model_delay_test.ok \
sky130/21_ngspice_delay_extra_rows_test.ok \
sky130/21_ngspice_delay_test.ok \
sky130/21_regression_delay_test.ok \
sky130/22_psram_1bank_2mux_func_test.ok \
sky130/22_psram_1bank_4mux_func_test.ok \
sky130/22_psram_1bank_8mux_func_test.ok \
@@ -107,54 +174,6 @@ BROKEN_STAMPS = \
sky130/23_lib_sram_model_test.ok \
sky130/23_lib_sram_prune_test.ok \
sky130/23_lib_sram_test.ok \
sky130/03_wire_test.ok \
sky130/04_dummy_pbitcell_1rw1r1w_test.ok \
sky130/04_dummy_pbitcell_1rw_test.ok \
sky130/04_replica_pbitcell_1rw1r1w_test.ok \
sky130/04_replica_pbitcell_1rw_test.ok \
sky130/06_hierarchical_decoder_132row_test.ok \
sky130/06_hierarchical_decoder_512row_test.ok \
sky130/06_hierarchical_decoder_64row_test.ok \
sky130/06_hierarchical_decoder_pbitcell_test.ok \
sky130/10_write_driver_array_spare_cols_test.ok \
sky130/10_write_driver_array_wmask_spare_cols_test.ok \
sky130/14_capped_replica_bitcell_array_leftrbl_1rw_test.ok \
sky130/14_capped_replica_bitcell_array_norbl_1rw_test.ok \
sky130/14_replica_bitcell_array_leftrbl_1rw_test.ok \
sky130/14_replica_bitcell_array_norbl_1rw_test.ok \
sky130/14_replica_column_1rw_1r_test.ok \
sky130/14_replica_column_1rw_test.ok \
sky130/14_replica_pbitcell_1rw1r_array_test.ok \
sky130/14_replica_pbitcell_1rw_array_test.ok \
sky130/15_global_bitcell_array_1rw_1r_test.ok \
sky130/15_global_bitcell_array_test.ok \
sky130/15_local_bitcell_array_test.ok \
sky130/18_port_address_512rows_test.ok \
sky130/18_port_data_spare_cols_test.ok \
sky130/19_single_bank_2mux_test.ok \
sky130/19_single_bank_4mux_test.ok \
sky130/19_single_bank_8mux_test.ok \
sky130/19_single_bank_global_bitline_test.ok \
sky130/19_single_bank_nomux_test.ok \
sky130/19_single_bank_spare_cols_test.ok \
sky130/19_single_bank_wmask_test.ok \
sky130/20_sram_1bank_2mux_1rw_1r_spare_cols_test.ok \
sky130/20_sram_1bank_2mux_1w_1r_spare_cols_test.ok \
sky130/20_sram_1bank_2mux_global_test.ok \
sky130/20_sram_1bank_2mux_test.ok \
sky130/20_sram_1bank_2mux_wmask_spare_cols_test.ok \
sky130/20_sram_1bank_2mux_wmask_test.ok \
sky130/20_sram_1bank_4mux_test.ok \
sky130/20_sram_1bank_8mux_test.ok \
sky130/20_sram_1bank_nomux_spare_cols_test.ok \
sky130/20_sram_1bank_nomux_test.ok \
sky130/20_sram_1bank_nomux_wmask_test.ok \
sky130/20_sram_1bank_ring_test.ok \
sky130/21_model_delay_test.ok \
sky130/21_ngspice_delay_extra_rows_test.ok \
sky130/21_ngspice_delay_test.ok \
sky130/21_regression_delay_test.ok \
sky130/21_xyce_delay_test.ok \
sky130/25_verilog_multibank_test.ok \
sky130/25_verilog_sram_test.ok \
sky130/30_openram_back_end_library_test.ok \