Merge branch 'dev' into bisr

compiler/tests/02_library_lvs_test.py

@@ -35,7 +35,7 @@ class library_lvs_test(openram_test):
                 debug.error("Missing GDS file {}".format(gds_name))
             if not os.path.isfile(sp_name):
                 lvs_errors += 1
-                debug.error("Missing SPICE file {}".format(gds_name))
+                debug.error("Missing SPICE file {}".format(sp_name))
             drc_errors += verify.run_drc(name, gds_name)
             lvs_errors += verify.run_lvs(f, gds_name, sp_name)
 

compiler/tests/04_and2_dec_test.py

@@ -0,0 +1,39 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class and2_dec_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        global verify
+        import verify
+
+        import and2_dec
+
+        debug.info(2, "Testing and2 gate 4x")
+        a = and2_dec.and2_dec(name="and2x4", size=4)
+        self.local_check(a)
+
+        globals.end_openram()
+
+# instantiate a copdsay of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/04_and3_dec_test.py

@@ -0,0 +1,39 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class and3_dec_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        global verify
+        import verify
+
+        import and3_dec
+
+        debug.info(2, "Testing and3 gate 4x")
+        a = and3_dec.and3_dec(name="and3x4", size=4)
+        self.local_check(a)
+
+        globals.end_openram()
+
+# instantiate a copdsay of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/04_and4_dec_test.py

@@ -0,0 +1,39 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class and3_dec_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        global verify
+        import verify
+
+        import and3_dec
+
+        debug.info(2, "Testing and3 gate 4x")
+        a = and3_dec.and3_dec(name="and3x4", size=4)
+        self.local_check(a)
+
+        globals.end_openram()
+
+# instantiate a copdsay of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/04_pand2_test.py

@@ -29,6 +29,10 @@ class pand2_test(openram_test):
         a = pand2.pand2(name="pand2x4", size=4)
         self.local_check(a)
 
+        debug.info(2, "Testing vertical pand2 gate 4x")
+        a = pand2.pand2(name="pand2x4", size=4, vertical=True)
+        self.local_check(a)
+        
         globals.end_openram()
 
 # instantiate a copdsay of the class to actually run the test

compiler/tests/04_pand3_test.py

@@ -29,6 +29,10 @@ class pand3_test(openram_test):
         a = pand3.pand3(name="pand3x4", size=4)
         self.local_check(a)
 
+        debug.info(2, "Testing vertical pand3 gate 4x")
+        a = pand3.pand3(name="pand3x4", size=4, vertical=True)
+        self.local_check(a)
+        
         globals.end_openram()
 
 # instantiate a copdsay of the class to actually run the test

compiler/tests/04_pdriver_test.py

@@ -32,13 +32,13 @@ class pdriver_test(openram_test):
         c = factory.create(module_type="pdriver", fanout = 50)
         self.local_check(c)
         
-        d = factory.create(module_type="pdriver", fanout = 50, neg_polarity = True)
+        d = factory.create(module_type="pdriver", fanout = 50, inverting = True)
         self.local_check(d)
         
         e = factory.create(module_type="pdriver", fanout = 64)
         self.local_check(e)
         
-        f = factory.create(module_type="pdriver", fanout = 64, neg_polarity = True)
+        f = factory.create(module_type="pdriver", fanout = 64, inverting = True)
         self.local_check(f)
 
         globals.end_openram()

compiler/tests/04_pinv_dec_1x_test.py

@@ -0,0 +1,35 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class pinv_dec_1x_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        debug.info(2, "Checking 1x size decoder inverter")
+        tx = factory.create(module_type="pinv_dec", size=1)
+        self.local_check(tx)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/04_pnand2_test.py

@@ -25,6 +25,11 @@ class pnand2_test(openram_test):
         tx = factory.create(module_type="pnand2", size=1)
         self.local_check(tx)
 
+        debug.info(2, "Checking 2-input nand gate")
+        tx = factory.create(module_type="pnand2", size=1, add_wells=False)
+        # Only DRC because well contacts will fail LVS
+        self.local_drc_check(tx)
+        
         globals.end_openram()
         
 

compiler/tests/04_pnand3_test.py

@@ -25,6 +25,11 @@ class pnand3_test(openram_test):
         tx = factory.create(module_type="pnand3", size=1)
         self.local_check(tx)
 
+        debug.info(2, "Checking 3-input nand gate")
+        tx = factory.create(module_type="pnand3", size=1, add_wells=False)
+        # Only DRC because well contacts will fail LVS
+        self.local_drc_check(tx)
+
         globals.end_openram()
         
 

compiler/tests/04_single_level_column_mux_1rw_1r_test.py

@@ -0,0 +1,45 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+class single_level_column_mux_1rw_1r_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+        
+        debug.info(2, "Checking column mux port 0")
+        tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
+        self.local_check(tx)
+
+        debug.info(2, "Checking column mux port 1")
+        tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl1", bitcell_br="br1")
+        self.local_check(tx)
+        
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/04_single_level_column_mux_test.py

@@ -15,7 +15,6 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-#@unittest.skip("SKIPPING 04_driver_test")
 
 class single_level_column_mux_test(openram_test):
 

compiler/tests/04_wordline_driver_test.py

@@ -25,7 +25,7 @@ class wordline_driver_test(openram_test):
 
         # check wordline driver for single port
         debug.info(2, "Checking driver")
-        tx = factory.create(module_type="wordline_driver", rows=8, cols=32)
+        tx = factory.create(module_type="wordline_driver")
         self.local_check(tx)
 
         globals.end_openram()

compiler/tests/05_bitcell_1rw_1r_array_test.py

@@ -23,12 +23,10 @@ class bitcell_1rw_1r_array_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         
-        OPTS.bitcell = "bitcell_1rw_1r"
-        OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
-        OPTS.dummy_bitcell="dummy_bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
+        globals.setup_bitcell()
         
         debug.info(2, "Testing 4x4 array for cell_1rw_1r")
         a = factory.create(module_type="bitcell_array", cols=4, rows=4)

compiler/tests/06_hierarchical_decoder_1rw_1r_test.py

@@ -0,0 +1,68 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+class hierarchical_decoder_1rw_1r_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # Use the 2 port cell since it is usually bigger/easier
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+        
+        # Checks 2x4 and 2-input NAND decoder
+        debug.info(1, "Testing 16 row sample for hierarchical_decoder")
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=16)
+        self.local_check(a)
+
+        # Checks 2x4 and 2-input NAND decoder with non-power-of-two
+        debug.info(1, "Testing 17 row sample for hierarchical_decoder")
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=17)
+        self.local_check(a)
+
+        # Checks 2x4 with 3x8 and 2-input NAND decoder
+        debug.info(1, "Testing 32 row sample for hierarchical_decoder")
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=32)
+        self.local_check(a)
+
+        # Checks 3 x 2x4 and 3-input NAND decoder
+        debug.info(1, "Testing 64 row sample for hierarchical_decoder")
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=64)
+        self.local_check(a)
+
+        # Checks 2x4 and 2 x 3x8 and 3-input NAND with non-power-of-two
+        debug.info(1, "Testing 132 row sample for hierarchical_decoder")
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=132)
+        self.local_check(a)
+
+        # Checks 3 x 3x8 and 3-input NAND decoder
+        debug.info(1, "Testing 512 row sample for hierarchical_decoder")
+        a = factory.create(module_type="hierarchical_decoder", num_outputs=512)
+        self.local_check(a)
+        
+        globals.end_openram()
+        
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/06_hierarchical_decoder_pbitcell_test.py

@@ -21,11 +21,11 @@ class hierarchical_decoder_pbitcell_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         # check hierarchical decoder for multi-port
-        OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 0
-
+        globals.setup_bitcell()
+        
         factory.reset()
         debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)")
         a = factory.create(module_type="hierarchical_decoder", num_outputs=16)

compiler/tests/06_hierarchical_decoder_test.py

@@ -25,7 +25,7 @@ class hierarchical_decoder_test(openram_test):
         debug.info(1, "Testing 16 row sample for hierarchical_decoder")
         a = factory.create(module_type="hierarchical_decoder", num_outputs=16)
         self.local_check(a)
-        
+
         # Checks 2x4 and 2-input NAND decoder with non-power-of-two
         debug.info(1, "Testing 17 row sample for hierarchical_decoder")
         a = factory.create(module_type="hierarchical_decoder", num_outputs=17)

compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py

@@ -1,7 +1,9 @@
 #!/usr/bin/env python3
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California 
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
 import unittest
@@ -13,21 +15,22 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-class replica_bitcell_array_test(openram_test):
+
+class hierarchical_predecode2x4_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
         OPTS.num_rw_ports = 1
-        OPTS.num_r_ports = 0
+        OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-
-        factory.reset()
-        debug.info(2, "Testing 4x4 array for bitcell")
-        a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=0, bitcell_ports=[0])
-        self.local_check(a)
+        globals.setup_bitcell()
         
+        debug.info(1, "Testing sample for hierarchy_predecode2x4")
+        a = factory.create(module_type="hierarchical_predecode2x4")
+        self.local_check(a)
+
         globals.end_openram()
 
 # run the test from the command line

compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py

@@ -22,11 +22,11 @@ class hierarchical_predecode2x4_pbitcell_test(openram_test):
         globals.init_openram(config_file)
 
         # checking hierarchical precode 2x4 for multi-port
-        OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 0
-
+        globals.setup_bitcell()
+        
         debug.info(1, "Testing sample for hierarchy_predecode2x4 (multi-port case)")
         a = factory.create(module_type="hierarchical_predecode2x4")
         self.local_check(a)

compiler/tests/06_hierarchical_predecode2x4_test.py

@@ -21,7 +21,6 @@ class hierarchical_predecode2x4_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
-        # checking hierarchical precode 2x4 for single port
         debug.info(1, "Testing sample for hierarchy_predecode2x4")
         a = factory.create(module_type="hierarchical_predecode2x4")
         self.local_check(a)

compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py

@@ -0,0 +1,42 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+class hierarchical_predecode3x8_1rw_1r_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # Use the 2 port cell since it is usually bigger/easier
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+        
+        debug.info(1, "Testing sample for hierarchy_predecode3x8")
+        a = factory.create(module_type="hierarchical_predecode3x8")
+        self.local_check(a)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py

@@ -22,11 +22,11 @@ class hierarchical_predecode3x8_pbitcell_test(openram_test):
         globals.init_openram(config_file)
 
         # checking hierarchical precode 3x8 for multi-port
-        OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 0
-
+        globals.setup_bitcell()
+        
         debug.info(1, "Testing sample for hierarchy_predecode3x8 (multi-port case)")
         a = factory.create(module_type="hierarchical_predecode3x8")
         self.local_check(a)

compiler/tests/06_hierarchical_predecode3x8_test.py

@@ -21,7 +21,6 @@ class hierarchical_predecode3x8_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
-        # checking hierarchical precode 3x8 for single port
         debug.info(1, "Testing sample for hierarchy_predecode3x8")
         a = factory.create(module_type="hierarchical_predecode3x8")
         self.local_check(a)

compiler/tests/06_hierarchical_predecode4x16_test.py

@@ -0,0 +1,42 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+@unittest.skip("SKIPPING hierarchical_predecode4x16_test")
+class hierarchical_predecode4x16_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # Use the 2 port cell since it is usually bigger/easier
+        OPTS.bitcell = "bitcell_1rw_1r"
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+
+        debug.info(1, "Testing sample for hierarchy_predecode4x16")
+        a = factory.create(module_type="hierarchical_predecode4x16")
+        self.local_check(a)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/07_single_level_column_mux_array_1rw_1r_test.py

@@ -0,0 +1,44 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class single_level_column_mux_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+        
+        debug.info(1, "Testing sample for 4-way column_mux_array port 0")
+        a = factory.create(module_type="single_level_column_mux_array", columns=8, word_size=2, bitcell_bl="bl0", bitcell_br="br0")
+        self.local_check(a)
+
+        debug.info(1, "Testing sample for 4-way column_mux_array port 1")
+        a = factory.create(module_type="single_level_column_mux_array", columns=8, word_size=2, bitcell_bl="bl1", bitcell_br="br1")
+        self.local_check(a)
+
+        globals.end_openram()
+
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/07_single_level_column_mux_array_pbitcell_test.py

@@ -41,7 +41,7 @@ class single_level_column_mux_pbitcell_test(openram_test):
         self.local_check(a)
 
         debug.info(1, "Testing sample for 8-way column_mux_array  in multi-port (outermost connections)")
-        a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2")
+        a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2", column_offset=3)
         self.local_check(a)
 
         globals.end_openram()

compiler/tests/07_single_level_column_mux_array_test.py

@@ -19,9 +19,7 @@ class single_level_column_mux_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
-        import single_level_column_mux_array
 
-        # check single level column mux array in single port
         debug.info(1, "Testing sample for 2-way column_mux_array")
         a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=8)
         self.local_check(a)

compiler/tests/08_precharge_array_1rw_1r_test.py

@@ -15,31 +15,27 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-class precharge_test(openram_test):
+class precharge_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         
         # check precharge array in multi-port
-        OPTS.bitcell = "bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
+        globals.setup_bitcell()
 
         factory.reset()
-        debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell")
+        debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell (port 0)")
         pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0")
         self.local_check(pc)
-        
-        # debug.info(2, "Checking 3 column precharge array for pbitcell (innermost connections)")
-        # pc = precharge_array.precharge_array(name="pre3", columns=3, bitcell_bl="bl0", bitcell_br="br0")
-        # self.local_check(pc)
-        
-        # debug.info(2, "Checking 3 column precharge array for pbitcell (outermost connections)")
-        # pc = precharge_array.precharge_array(name="pre4", columns=3, bitcell_bl="bl2", bitcell_br="br2")
-        # self.local_check(pc)
 
+        debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell (port 1)")
+        pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0", column_offset=1)
+        self.local_check(pc)
+        
         globals.end_openram()
 
 # run the test from the command line

compiler/tests/08_precharge_array_test.py

@@ -21,7 +21,6 @@ class precharge_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
-        # check precharge array in single port
         debug.info(2, "Checking 3 column precharge")
         pc = factory.create(module_type="precharge_array", columns=3)
         self.local_check(pc)

compiler/tests/08_wordline_driver_array_1rw_1r_test.py

@@ -0,0 +1,43 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+class wordline_driver_array_1rw_1r_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # Use the 2 port cell since it is usually bigger/easier
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+
+        # check wordline driver for single port
+        debug.info(2, "Checking driver")
+        tx = factory.create(module_type="wordline_driver_array", rows=8, cols=32)
+        self.local_check(tx)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/08_wordline_driver_array_pbitcell_test.py

@@ -15,9 +15,8 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-#@unittest.skip("SKIPPING 04_driver_test")
 
-class wordline_driver_pbitcell_test(openram_test):
+class wordline_driver_array_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -31,7 +30,7 @@ class wordline_driver_pbitcell_test(openram_test):
 
         factory.reset()
         debug.info(2, "Checking driver (multi-port case)")
-        tx = factory.create(module_type="wordline_driver", rows=8, cols=64)
+        tx = factory.create(module_type="wordline_driver_array", rows=8, cols=64)
         self.local_check(tx)
 
         globals.end_openram()

compiler/tests/08_wordline_driver_array_test.py

@@ -0,0 +1,37 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+class wordline_driver_array_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # check wordline driver for single port
+        debug.info(2, "Checking driver")
+        tx = factory.create(module_type="wordline_driver_array", rows=8, cols=32)
+        self.local_check(tx)
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/09_sense_amp_array_test.py

@@ -21,7 +21,6 @@ class sense_amp_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
-        # check sense amp array for single port
         debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=1")
         a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=1)
         self.local_check(a)

compiler/tests/14_replica_bitcell_1rw_1r_array_test.py

@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California 
+# Copyright (c) 2016-2019 Regents of the University of California
 # All rights reserved.
 #
 import unittest
@@ -19,19 +19,17 @@ class replica_bitcell_array_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
-        OPTS.bitcell = "bitcell_1rw_1r"
-        OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
-        OPTS.dummy_bitcell="dummy_bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
+        globals.setup_bitcell()
         
         debug.info(2, "Testing 4x4 array for cell_1rw_1r")
-        a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=2, right_rbl=0, bitcell_ports=[0,1])
+        a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=1, bitcell_ports=[0, 1])
         self.local_check(a)
 
         debug.info(2, "Testing 4x4 array for cell_1rw_1r")
-        a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=1, bitcell_ports=[0,1])
+        a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=2, right_rbl=0, bitcell_ports=[0, 1])
         self.local_check(a)
 
         globals.end_openram()

compiler/tests/14_replica_bitcell_array_test.py

@@ -19,10 +19,15 @@ class replica_bitcell_array_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
 
-        debug.info(2, "Testing 4x4 array for 6t_cell")
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 0
+        OPTS.num_w_ports = 0
+
+        factory.reset()
+        debug.info(2, "Testing 4x4 array for bitcell")
         a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=0, bitcell_ports=[0])
         self.local_check(a)
-
+        
         globals.end_openram()
 
 # run the test from the command line

compiler/tests/18_port_address_1rw_1r_test.py

@@ -0,0 +1,44 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+class port_address_1rw_1r_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+
+        # Use the 2 port cell since it is usually bigger/easier
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+        
+        debug.info(1, "Port address 16 rows")
+        a = factory.create("port_address", cols=16, rows=16)
+        self.local_check(a)
+
+        debug.info(1, "Port address 512 rows")
+        a = factory.create("port_address", cols=256, rows=512)
+        self.local_check(a)
+        
+        globals.end_openram()
+        
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/18_port_address_test.py

@@ -13,6 +13,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
+
 class port_address_test(openram_test):
 
     def runTest(self):
@@ -23,6 +24,10 @@ class port_address_test(openram_test):
         a = factory.create("port_address", cols=16, rows=16)
         self.local_check(a)
         
+        debug.info(1, "Port address 512 rows")
+        a = factory.create("port_address", cols=256, rows=512)
+        self.local_check(a)
+
         globals.end_openram()
         
 # run the test from the command line

compiler/tests/18_port_data_1rw_1r_test.py

@@ -13,6 +13,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
+
 class port_data_1rw_1r_test(openram_test):
 
     def runTest(self):
@@ -20,11 +21,11 @@ class port_data_1rw_1r_test(openram_test):
         globals.init_openram(config_file)
         from sram_config import sram_config
 
-        OPTS.bitcell = "bitcell_1w_1r"
-        OPTS.num_rw_ports = 0
+        OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
-        OPTS.num_w_ports = 1
-
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+        
         c = sram_config(word_size=4,
                         num_words=16)
 
@@ -36,7 +37,7 @@ class port_data_1rw_1r_test(openram_test):
         self.local_check(a)
         a = factory.create("port_data", sram_config=c, port=1)
         self.local_check(a)
-        
+
         c.num_words=32
         c.words_per_row=2
         factory.reset()

compiler/tests/19_single_bank_1rw_1r_test.py

@@ -22,12 +22,10 @@ class single_bank_1rw_1r_test(openram_test):
         globals.init_openram(config_file)
         from sram_config import sram_config
 
-        OPTS.bitcell = "bitcell_1rw_1r"
-        OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
-        OPTS.dummy_bitcell="dummy_bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
+        globals.setup_bitcell()
         
         c = sram_config(word_size=4,
                         num_words=16)

compiler/tests/19_single_bank_1w_1r_test.py

@@ -22,13 +22,10 @@ class single_bank_1w_1r_test(openram_test):
         globals.init_openram(config_file)
         from sram_config import sram_config
 
-        OPTS.bitcell = "bitcell_1w_1r"
-        OPTS.replica_bitcell = "replica_bitcell_1w_1r"
-        OPTS.dummy_bitcell="dummy_bitcell_1w_1r"
-
         OPTS.num_rw_ports = 0
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 1
+        globals.setup_bitcell()
         
         c = sram_config(word_size=4,
                         num_words=16)

compiler/tests/19_single_bank_test.py

@@ -25,28 +25,28 @@ class single_bank_test(openram_test):
         c = sram_config(word_size=4,
                         num_words=16)
 
-        # c.words_per_row=1
-        # factory.reset()
-        # c.recompute_sizes()
-        # debug.info(1, "No column mux")
-        # a = factory.create("bank", sram_config=c)
-        # self.local_check(a)
+        c.words_per_row=1
+        factory.reset()
+        c.recompute_sizes()
+        debug.info(1, "No column mux")
+        a = factory.create("bank", sram_config=c)
+        self.local_check(a)
 
-        # c.num_words=32
-        # c.words_per_row=2
-        # factory.reset()
-        # c.recompute_sizes()
-        # debug.info(1, "Two way column mux")
-        # a = factory.create("bank", sram_config=c)
-        # self.local_check(a)
+        c.num_words=32
+        c.words_per_row=2
+        factory.reset()
+        c.recompute_sizes()
+        debug.info(1, "Two way column mux")
+        a = factory.create("bank", sram_config=c)
+        self.local_check(a)
 
-        # c.num_words=64
-        # c.words_per_row=4
-        # factory.reset()
-        # c.recompute_sizes()
-        # debug.info(1, "Four way column mux")
-        # a = factory.create("bank", sram_config=c)
-        # self.local_check(a)
+        c.num_words=64
+        c.words_per_row=4
+        factory.reset()
+        c.recompute_sizes()
+        debug.info(1, "Four way column mux")
+        a = factory.create("bank", sram_config=c)
+        self.local_check(a)
 
         c.word_size=2
         c.num_words=128

compiler/tests/19_single_bank_wmask_1rw_1r_test.py

@@ -0,0 +1,73 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class single_bank_wmask_1rw_1r_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        from sram_config import sram_config
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+
+        c = sram_config(word_size=8,
+                        write_size=4,
+                        num_words=16,
+                        num_banks=1)
+
+        c.words_per_row=1
+        factory.reset()
+        c.recompute_sizes()
+        debug.info(1, "No column mux")
+        a = factory.create("bank", sram_config=c)
+        self.local_check(a)
+
+        c.num_words=32
+        c.words_per_row=2
+        factory.reset()
+        c.recompute_sizes()
+        debug.info(1, "Two way column mux")
+        a = factory.create("bank", sram_config=c)
+        self.local_check(a)
+
+        c.num_words=64
+        c.words_per_row=4
+        factory.reset()
+        c.recompute_sizes()
+        debug.info(1, "Four way column mux")
+        a = factory.create("bank", sram_config=c)
+        self.local_check(a)
+
+        c.num_words=128
+        c.words_per_row=8
+        factory.reset()
+        c.recompute_sizes()
+        debug.info(1, "Eight way column mux")
+        a = factory.create("bank", sram_config=c)
+        self.local_check(a)
+        
+        globals.end_openram()
+        
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py

@@ -24,11 +24,10 @@ class psram_1bank_2mux_1rw_1w_test(openram_test):
         from sram_config import sram_config
 
         OPTS.bitcell = "pbitcell"
-        OPTS.replica_bitcell="replica_pbitcell"
-        OPTS.dummy_bitcell="dummy_pbitcell"
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 1
         OPTS.num_r_ports = 0
+        globals.setup_bitcell()
         
         c = sram_config(word_size=4,
                         num_words=32,

compiler/tests/20_psram_1bank_2mux_1w_1r_test.py

@@ -24,11 +24,10 @@ class psram_1bank_2mux_1w_1r_test(openram_test):
         from sram_config import sram_config
 
         OPTS.bitcell = "pbitcell"
-        OPTS.replica_bitcell="replica_pbitcell"
-        OPTS.dummy_bitcell="dummy_pbitcell"
         OPTS.num_rw_ports = 0
         OPTS.num_w_ports = 1
         OPTS.num_r_ports = 1
+        globals.setup_bitcell()
         
         c = sram_config(word_size=4,
                         num_words=32,

compiler/tests/20_psram_1bank_2mux_test.py

@@ -22,14 +22,12 @@ class psram_1bank_2mux_test(openram_test):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
         globals.init_openram(config_file)
         from sram_config import sram_config
-        OPTS.bitcell = "pbitcell"
-        OPTS.replica_bitcell="replica_pbitcell"
-        OPTS.dummy_bitcell="dummy_pbitcell"        
         
-        # testing layout of sram using pbitcell with 1 RW port (a 6T-cell equivalent)
+        OPTS.bitcell = "pbitcell"
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 0
+        globals.setup_bitcell()
         
         c = sram_config(word_size=4,
                         num_words=32,

compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py

@@ -24,11 +24,10 @@ class psram_1bank_4mux_1rw_1r_test(openram_test):
         from sram_config import sram_config
 
         OPTS.bitcell = "pbitcell"
-        OPTS.replica_bitcell="replica_pbitcell"
-        OPTS.dummy_bitcell="dummy_pbitcell"        
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 1
+        globals.setup_bitcell()
         
         c = sram_config(word_size=4,
                         num_words=64,

compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py

@@ -22,12 +22,10 @@ class sram_1bank_2mux_1rw_1r_test(openram_test):
         globals.init_openram(config_file)
         from sram_config import sram_config
         
-        OPTS.bitcell = "bitcell_1rw_1r"
-        OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
-        OPTS.dummy_bitcell="dummy_bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
+        globals.setup_bitcell()
         
         c = sram_config(word_size=4,
                         num_words=32,

compiler/tests/20_sram_1bank_2mux_1w_1r_test.py

@@ -23,12 +23,10 @@ class psram_1bank_2mux_1w_1r_test(openram_test):
         globals.init_openram(config_file)
         from sram_config import sram_config
         
-        OPTS.bitcell = "bitcell_1w_1r"
-        OPTS.replica_bitcell="replica_bitcell_1w_1r"
-        OPTS.dummy_bitcell="dummy_bitcell_1w_1r"
         OPTS.num_rw_ports = 0
         OPTS.num_w_ports = 1
         OPTS.num_r_ports = 1
+        globals.setup_bitcell()
         
         c = sram_config(word_size=4,
                         num_words=32,

compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py

@@ -22,13 +22,11 @@ class sram_1bank_8mux_1rw_1r_test(openram_test):
         globals.init_openram(config_file)
         from sram_config import sram_config
 
-        OPTS.bitcell = "bitcell_1rw_1r"
-        OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
-        OPTS.dummy_bitcell="dummy_bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
-
+        globals.setup_bitcell()
+        
         c = sram_config(word_size=2,
                         num_words=128,
                         num_banks=1)

compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py

@@ -22,12 +22,10 @@ class sram_1bank_nomux_1rw_1r_test(openram_test):
         globals.init_openram(config_file)
         from sram_config import sram_config
         
-        OPTS.bitcell = "bitcell_1rw_1r"
-        OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
-        OPTS.dummy_bitcell = "dummy_bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0
+        globals.setup_bitcell()
         
         c = sram_config(word_size=4,
                         num_words=16,

compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py

@@ -24,12 +24,10 @@ class psram_1bank_nomux_func_test(openram_test):
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
-        OPTS.bitcell = "bitcell_1rw_1r"
-        OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
-        OPTS.dummy_bitcell="dummy_bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 1
+        globals.setup_bitcell()
         
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload

compiler/tests/22_sram_wmask_1w_1r_func_test.py

@@ -26,14 +26,11 @@ class sram_wmask_1w_1r_func_test(openram_test):
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
-        OPTS.bitcell = "bitcell_1w_1r"
-        OPTS.replica_bitcell = "replica_bitcell_1w_1r"
-        OPTS.dummy_bitcell = "dummy_bitcell_1w_1r"
-
         OPTS.num_rw_ports = 0
         OPTS.num_w_ports = 1
         OPTS.num_r_ports = 1
-
+        globals.setup_bitcell()
+        
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
         import characterizer

compiler/tests/testutils.py

@@ -5,23 +5,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import unittest,warnings
-import pdb,traceback
-import sys,os,glob,copy
-import shutil
+import unittest
+import sys, os, glob
 sys.path.append(os.getenv("OPENRAM_HOME"))
 from globals import OPTS
 import debug
 
+
 class openram_test(unittest.TestCase):
     """ Base unit test that we have some shared classes in. """
 
-
     def local_drc_check(self, w):
 
         self.reset()
 
-        tempgds = "{0}{1}.gds".format(OPTS.openram_temp,w.name)
+        tempgds = "{0}{1}.gds".format(OPTS.openram_temp, w.name)
         w.gds_write(tempgds)
         import verify
 
@@ -36,8 +34,8 @@ class openram_test(unittest.TestCase):
 
         self.reset()
 
-        tempspice = "{0}{1}.sp".format(OPTS.openram_temp,a.name)
-        tempgds = "{0}{1}.gds".format(OPTS.openram_temp,a.name)
+        tempspice = "{0}{1}.sp".format(OPTS.openram_temp, a.name)
+        tempgds = "{0}{1}.gds".format(OPTS.openram_temp, a.name)
 
         a.lvs_write(tempspice)
         # cannot write gds in netlist_only mode
@@ -56,33 +54,36 @@ class openram_test(unittest.TestCase):
                 
             # Only allow DRC to fail and LVS to pass if we are using magic
             if "magic" in OPTS.drc_exe and lvs_result == 0 and drc_result != 0:
-                #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid())
-                #debug.info(0,"Archiving failed files to {}.zip".format(zip_file))
-                #shutil.make_archive(zip_file, 'zip', OPTS.openram_temp)
+                # import shutil
+                # zip_file = "/tmp/{0}_{1}".format(a.name, os.getpid())
+                # debug.info(0, "Archiving failed files to {}.zip".format(zip_file))
+                # shutil.make_archive(zip_file, 'zip', OPTS.openram_temp)
                 debug.warning("DRC failed but LVS passed: {}".format(a.name))
+                # self.fail("DRC failed but LVS passed: {}".format(a.name))
             elif drc_result != 0:
-                #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid())
-                #debug.info(0,"Archiving failed files to {}.zip".format(zip_file))
-                #shutil.make_archive(zip_file, 'zip', OPTS.openram_temp)
+                # import shutil
+                # zip_file = "/tmp/{0}_{1}".format(a.name, os.getpid())
+                # debug.info(0,"Archiving failed files to {}.zip".format(zip_file))
+                # shutil.make_archive(zip_file, 'zip', OPTS.openram_temp)
                 self.fail("DRC failed: {}".format(a.name))
                 
             if lvs_result != 0:
-                #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid())
-                #debug.info(0,"Archiving failed files to {}.zip".format(zip_file))
-                #shutil.make_archive(zip_file, 'zip', OPTS.openram_temp)
+                # import shutil
+                # zip_file = "/tmp/{0}_{1}".format(a.name, os.getpid())
+                # debug.info(0,"Archiving failed files to {}.zip".format(zip_file))
+                # shutil.make_archive(zip_file, 'zip', OPTS.openram_temp)
                 self.fail("LVS mismatch: {}".format(a.name))
 
-
         # For debug...
-        #import pdb; pdb.set_trace()
+        # import pdb; pdb.set_trace()
         if OPTS.purge_temp:
             self.cleanup()
 
     def run_pex(self, a, output=None):
         if output == None:
             output = OPTS.openram_temp + a.name + ".pex.netlist"
-        tempspice = "{0}{1}.sp".format(OPTS.openram_temp,a.name)
-        tempgds = "{0}{1}.gds".format(OPTS.openram_temp,a.name)
+        tempspice = "{0}{1}.sp".format(OPTS.openram_temp, a.name)
+        tempgds = "{0}{1}.gds".format(OPTS.openram_temp, a.name)
 
         import verify
         result=verify.run_pex(a.name, tempgds, tempspice, output=output, final_verification=False)
@@ -96,8 +97,8 @@ class openram_test(unittest.TestCase):
         """
         debug.info(1, "Finding feasible period for current test.")
         delay_obj.set_load_slew(load, slew)
-        test_port = delay_obj.read_ports[0] #Only test one port, assumes other ports have similar period.
-        delay_obj.analysis_init(probe_address="1"*sram.addr_size, probe_data=(sram.word_size-1))
+        test_port = delay_obj.read_ports[0] # Only test one port, assumes other ports have similar period.
+        delay_obj.analysis_init(probe_address="1" * sram.addr_size, probe_data=sram.word_size - 1)
         delay_obj.find_feasible_period_one_port(test_port)
         return delay_obj.period
 
@@ -129,29 +130,27 @@ class openram_test(unittest.TestCase):
         for k in data.keys():
             if type(data[k])==list:
                 for i in range(len(data[k])):
-                    if not self.isclose(k,data[k][i],golden_data[k][i],error_tolerance):
+                    if not self.isclose(k, data[k][i], golden_data[k][i], error_tolerance):
                         data_matches = False
             else:
-                if not self.isclose(k,data[k],golden_data[k],error_tolerance):
+                if not self.isclose(k, data[k], golden_data[k], error_tolerance):
                     data_matches = False
         if not data_matches:
             import pprint
             data_string=pprint.pformat(data)
-            debug.error("Results exceeded {:.1f}% tolerance compared to golden results:\n".format(error_tolerance*100)+data_string)
+            debug.error("Results exceeded {:.1f}% tolerance compared to golden results:\n".format(error_tolerance * 100) + data_string)
         return data_matches
 
-
-
-    def isclose(self,key,value,actual_value,error_tolerance=1e-2):
+    def isclose(self, key, value, actual_value, error_tolerance=1e-2):
         """ This is used to compare relative values. """
         import debug
-        relative_diff = self.relative_diff(value,actual_value)
+        relative_diff = self.relative_diff(value, actual_value)
         check = relative_diff <= error_tolerance
         if check:
-            debug.info(2,"CLOSE\t{0: <10}\t{1:.3f}\t{2:.3f}\tdiff={3:.1f}%".format(key,value,actual_value,relative_diff*100))
+            debug.info(2, "CLOSE\t{0: <10}\t{1:.3f}\t{2:.3f}\tdiff={3:.1f}%".format(key, value, actual_value, relative_diff * 100))
             return True
         else:
-            debug.error("NOT CLOSE\t{0: <10}\t{1:.3f}\t{2:.3f}\tdiff={3:.1f}%".format(key,value,actual_value,relative_diff*100))
+            debug.error("NOT CLOSE\t{0: <10}\t{1:.3f}\t{2:.3f}\tdiff={3:.1f}%".format(key, value, actual_value, relative_diff * 100))
             return False
 
     def relative_diff(self, value1, value2):
@@ -168,18 +167,14 @@ class openram_test(unittest.TestCase):
 
         # Get normalization value
         norm_value = abs(max(value1, value2))
-        # Edge case where greater is a zero
-        if norm_value == 0:
-            min_value = abs(min(value1, value2))
 
         return abs(value1 - value2) / norm_value
 
-
-    def relative_compare(self, value,actual_value,error_tolerance):
+    def relative_compare(self, value, actual_value, error_tolerance):
         """ This is used to compare relative values. """
         if (value==actual_value): # if we don't need a relative comparison!
             return True
-        return (abs(value - actual_value) / max(value,actual_value) <= error_tolerance)
+        return (abs(value - actual_value) / max(value, actual_value) <= error_tolerance)
 
     def isapproxdiff(self, filename1, filename2, error_tolerance=0.001):
         """Compare two files.
@@ -217,23 +212,22 @@ class openram_test(unittest.TestCase):
             line_num+=1
             line1 = fp1.readline().decode('utf-8')
             line2 = fp2.readline().decode('utf-8')
-            #print("line1:",line1)
-            #print("line2:",line2)
+            # print("line1:", line1)
+            # print("line2:", line2)
 
             # 1. Find all of the floats using a regex
             line1_floats=rx.findall(line1)
             line2_floats=rx.findall(line2)
-            debug.info(3,"line1_floats: "+str(line1_floats))
-            debug.info(3,"line2_floats: "+str(line2_floats))
-
+            debug.info(3, "line1_floats: " + str(line1_floats))
+            debug.info(3, "line2_floats: " + str(line2_floats))
 
             # 2. Remove the floats from the string
             for f in line1_floats:
-                line1=line1.replace(f,"",1)
+                line1=line1.replace(f, "", 1)
             for f in line2_floats:
-                line2=line2.replace(f,"",1)
-            #print("line1:",line1)
-            #print("line2:",line2)
+                line2=line2.replace(f, "", 1)
+            # print("line1:", line1)
+            # print("line2:", line2)
 
             # 3. Convert to floats rather than strings
             line1_floats = [float(x) for x in line1_floats]
@@ -241,29 +235,29 @@ class openram_test(unittest.TestCase):
 
             # 4. Check if remaining string matches
             if line1 != line2:
-                #Uncomment if you want to see all the individual chars of the two lines
-                #print(str([i for i in line1]))
-                #print(str([i for i in line2]))
+                # Uncomment if you want to see all the individual chars of the two lines
+                # print(str([i for i in line1]))
+                # print(str([i for i in line2]))
                 if mismatches==0:
-                    debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1,filename2))
+                    debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1, filename2))
                 mismatches += 1
-                debug.error("MISMATCH Line ({0}):\n{1}\n!=\n{2}".format(line_num,line1.rstrip('\n'),line2.rstrip('\n')))
+                debug.error("MISMATCH Line ({0}):\n{1}\n!=\n{2}".format(line_num, line1.rstrip('\n'), line2.rstrip('\n')))
 
             # 5. Now compare that the floats match
             elif len(line1_floats)!=len(line2_floats):
                 if mismatches==0:
-                    debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1,filename2))
+                    debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1, filename2))
                 mismatches += 1
-                debug.error("MISMATCH Line ({0}) Length {1} != {2}".format(line_num,len(line1_floats),len(line2_floats)))
+                debug.error("MISMATCH Line ({0}) Length {1} != {2}".format(line_num, len(line1_floats), len(line2_floats)))
             else:
-                for (float1,float2) in zip(line1_floats,line2_floats):
-                    relative_diff = self.relative_diff(float1,float2)
+                for (float1, float2) in zip(line1_floats, line2_floats):
+                    relative_diff = self.relative_diff(float1, float2)
                     check = relative_diff <= error_tolerance
                     if not check:
                         if mismatches==0:
-                            debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1,filename2))
+                            debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1, filename2))
                         mismatches += 1
-                        debug.error("MISMATCH Line ({0}) Float {1} != {2} diff: {3:.1f}%".format(line_num,float1,float2,relative_diff*100))
+                        debug.error("MISMATCH Line ({0}) Float {1} != {2} diff: {3:.1f}%".format(line_num, float1, float2, relative_diff * 100))
 
             # Only show the first 10 mismatch lines
             if not line1 and not line2 or mismatches>10:
@@ -274,19 +268,18 @@ class openram_test(unittest.TestCase):
         # Never reached
         return False
 
-
-    def isdiff(self,filename1,filename2):
+    def isdiff(self, filename1, filename2):
         """ This is used to compare two files and display the diff if they are different.. """
         import debug
         import filecmp
         import difflib
-        check = filecmp.cmp(filename1,filename2)
+        check = filecmp.cmp(filename1, filename2)
         if not check:
-            debug.error("MISMATCH file1={0} file2={1}".format(filename1,filename2))
-            f1 = open(filename1,mode="r",encoding='utf-8')
+            debug.error("MISMATCH file1={0} file2={1}".format(filename1, filename2))
+            f1 = open(filename1, mode="r", encoding='utf-8')
             s1 = f1.readlines()
             f1.close()
-            f2 = open(filename2,mode="r",encoding='utf-8')
+            f2 = open(filename2, mode="r", encoding='utf-8')
             s2 = f2.readlines()
             f2.close()
             mismatches=0
@@ -301,10 +294,13 @@ class openram_test(unittest.TestCase):
                     return False
             return False
         else:
-            debug.info(2,"MATCH {0} {1}".format(filename1,filename2))
+            debug.info(2, "MATCH {0} {1}".format(filename1, filename2))
         return True
 
+    def dbg():
+        import pdb; pdb.set_trace()
 
+        
 def header(filename, technology):
     # Skip the header for gitlab regression
     import getpass
@@ -318,14 +314,18 @@ def header(filename, technology):
     print("|=========" + tst.center(60) + "=========|")
     print("|=========" + technology.center(60) + "=========|")
     print("|=========" + filename.center(60) + "=========|")
-    from  globals import OPTS
+    from globals import OPTS
     print("|=========" + OPTS.openram_temp.center(60) + "=========|")
     print("|==============================================================================|")
 
+    
 def debugTestRunner(post_mortem=None):
     """unittest runner doing post mortem debugging on failing tests"""
+    import pdb
+    import traceback
     if post_mortem is None and not OPTS.purge_temp:
         post_mortem = pdb.post_mortem
+        
     class DebugTestResult(unittest.TextTestResult):
         def addError(self, test, err):
             # called before tearDown()
@@ -333,9 +333,10 @@ def debugTestRunner(post_mortem=None):
             if post_mortem:
                 post_mortem(err[2])
             super(DebugTestResult, self).addError(test, err)
+            
         def addFailure(self, test, err):
             traceback.print_exception(*err)
-            if post_mortem:            
+            if post_mortem:
                 post_mortem(err[2])
             super(DebugTestResult, self).addFailure(test, err)
     return unittest.TextTestRunner(resultclass=DebugTestResult)