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Merge branch 'dev' into bisr

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This commit is contained in:
Aditi Sinha
2020-06-07 16:27:25 +00:00
parent eb0c595dbe 5d5ed552e3
commit d5041afebc
117 changed files with 3547 additions and 1285 deletions
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compiler/sram/sram_1bank.py
+4 -2
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@@ -189,7 +189,7 @@ class sram_1bank(sram_base):
if self.num_spare_cols:
spare_wen_pos[port] = vector(self.bank.bank_array_ur.x - self.wmask_dff_insts[port].width
- self.spare_wen_dff_insts[port].width - self.bank.m2_gap,
self.bank.height + bus_size + self.dff.height))
self.bank.height + bus_size + self.dff.height)
self.spare_wen_dff_insts[port].place(spare_wen_pos[port], mirror="MX")
# Place dffs when spare cols is enabled
@@ -400,7 +400,9 @@ class sram_1bank(sram_base):
# Only input (besides pins) is the replica bitline
src_pin = self.control_logic_insts[port].get_pin("rbl_bl")
dest_pin = self.bank_inst.get_pin("rbl_bl{}".format(port))
self.connect_hbus(src_pin, dest_pin)
self.add_wire(self.m2_stack[::-1],
[src_pin.center(), vector(src_pin.cx(), dest_pin.cy()), dest_pin.rc()])
# self.connect_hbus(src_pin, dest_pin)
def route_row_addr_dff(self):
""" Connect the output of the row flops to the bank pins """