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Merge branch 'dev' into bisr
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@@ -18,7 +18,8 @@ class write_driver_array(design.design):
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Dynamically generated write driver array of all bitlines.
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"""
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def __init__(self, name, columns, word_size, num_spare_cols=None, write_size=None):
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def __init__(self, name, columns, word_size, num_spare_cols=None, write_size=None, column_offset=0):
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design.design.__init__(self, name)
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debug.info(1, "Creating {0}".format(self.name))
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self.add_comment("columns: {0}".format(columns))
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@@ -27,6 +28,7 @@ class write_driver_array(design.design):
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self.columns = columns
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self.word_size = word_size
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self.write_size = write_size
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self.column_offset = column_offset
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self.words_per_row = int(columns / word_size)
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if not num_spare_cols:
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self.num_spare_cols = 0
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@@ -162,7 +164,7 @@ class write_driver_array(design.design):
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index = int(i / self.words_per_row)
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xoffset = i * self.driver_spacing
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if cell_properties.bitcell.mirror.y and i % 2:
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if cell_properties.bitcell.mirror.y and (i + self.column_offset) % 2:
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mirror = "MY"
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xoffset = xoffset + self.driver.width
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else:
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@@ -176,7 +178,7 @@ class write_driver_array(design.design):
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index = self.word_size + i
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xoffset = (self.columns + i) * self.driver_spacing
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if cell_properties.bitcell.mirror.y and i % 2:
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if cell_properties.bitcell.mirror.y and (i + self.column_offset) % 2:
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mirror = "MY"
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xoffset = xoffset + self.driver.width
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else:
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