luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-31 18:25:18 +02:00
Code Issues Packages Projects Releases Wiki Activity

Added power calculations for inverter. Still testing.

Browse Source
This commit is contained in:
Hunter Nichols
2018-02-21 19:51:21 -08:00
parent 179a27b0e3
commit d4a0f48d4f
10 changed files with 101 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/bank.py
+13 -13
View File
@@ -1229,22 +1229,22 @@ class bank(design.design):
+ bitcell_array_delay + bl_t_data_out_delay + data_t_DATA_delay
return result
def analytical_power(self, slew, load):
""" return analytical power of the bank. Basic skeleton code"""
msf_addr_power = self.msf_address.analytical_power(slew, self.decoder.input_load())
msf_data_in_power = self.msf_data_in.analytical_power(slew, self.decoder.input_load())
# def analytical_power(self, slew, load):
# """ return analytical power of the bank. Basic skeleton code"""
# msf_addr_power = self.msf_address.analytical_power(slew, self.decoder.input_load())
# msf_data_in_power = self.msf_data_in.analytical_power(slew, self.decoder.input_load())
decoder_power = self.decoder.analytical_power(slew, load)
# decoder_power = self.decoder.analytical_power(slew, load)
word_driver_power = self.wordline_driver.analytical_power(slew, self.bitcell_array.input_load())
# word_driver_power = self.wordline_driver.analytical_power(slew, self.bitcell_array.input_load())
bitcell_array_power = self.bitcell_array.analytical_power(slew)
# bitcell_array_power = self.bitcell_array.analytical_power(slew)
bl_t_data_out_power = self.sense_amp_array.analytical_power(slew,
self.bitcell_array.output_load())
# bl_t_data_out_power = self.sense_amp_array.analytical_power(slew,
# self.bitcell_array.output_load())
data_t_DATA_power = self.tri_gate_array.analytical_power(slew, load)
# data_t_DATA_power = self.tri_gate_array.analytical_power(slew, load)
total_power = msf_addr_power + msf_data_in_power + decoder_power + word_driver_power \
+ bitcell_array_power + bl_t_data_out_power + data_t_DATA_power
return total_power
# total_power = msf_addr_power + msf_data_in_power + decoder_power + word_driver_power \
# + bitcell_array_power + bl_t_data_out_power + data_t_DATA_power
# return total_power
compiler/modules/control_logic.py
+5 -3
View File
@@ -688,8 +688,10 @@ class control_logic(design.design):
width=pin.width())
def analytical_power(self, slew, load):
def analytical_power(self, vdd, temp, load):
#This has yet to be fully determined.
msf_power = self.msf_control.analytical_power(slew, load)
print "Instances:"
for inst in self.insts:
print inst.name," Instance"
#currently, only return flop array power
return msf_power
return 0