Added power calculations for inverter. Still testing.

compiler/base/design.py

@@ -122,6 +122,9 @@ class design(hierarchy_spice.spice, hierarchy_layout.layout):
         return text
      
     def analytical_power(self, slew, load):
-        #This function is here return 0 power for every module that does not have a power function defined
-        #This is a hack and should be made better (also may be a little dangerous)
-        return 0
+        """ Get total power of a module  """
+        #print "Getting power for ",self.name," module"
+        total_module_power = 0 
+        for inst in self.insts:
+            total_module_power += inst.mod.analytical_power(slew, load)
+        return total_module_power

compiler/base/hierarchy_spice.py

@@ -214,6 +214,9 @@ class spice(verilog.verilog):
 
     def generate_rc_net(self,lump_num, wire_length, wire_width):
         return wire_spice_model(lump_num, wire_length, wire_width)
+        
+    def return_power(self, dynamic, leakage):
+        return power_data(dynamic, leakage)
 
 class delay_data:
     """
@@ -246,6 +249,37 @@ class delay_data:
         assert isinstance(other,delay_data)
         return delay_data(other.delay + self.delay,
                           self.slew)
+                          
+class power_data:
+    """
+    This is the power class to represent the power information
+    Dynamic and leakage power are stored as a single object with this class.
+    """
+    def __init__(self, dynamic=0.0, leakage=0.0):
+        """ init function support two init method"""
+        # will take single input as a coordinate
+        self.dynamic = dynamic
+        self.leakage = leakage
+
+    def __str__(self):
+        """ override print function output """
+        return "Power Data: Dynamic "+str(self.dynamic)+", Leakage "+str(self.leakage)+" in nW"
+
+    def __add__(self, other):
+        """
+        Override - function (left), for power_data: a+b != b+a
+        """
+        assert isinstance(other,power_data)
+        return delay_data(other.dynamic + self.dynamic,
+                          other.leakage + self.leakage)
+
+    def __radd__(self, other):
+        """
+        Override - function (left), for power_data: a+b != b+a
+        """
+        assert isinstance(other,power_data)
+        return delay_data(other.dynamic + self.dynamic,
+                          other.leakage + self.leakage)
 
 
 class wire_spice_model: