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standardize rbl arguments interface

This commit is contained in:
samuelkcrow 2023-01-18 22:43:37 -08:00
parent 78c4ba5fc0
commit d460eacfcc
2 changed files with 5 additions and 10 deletions
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12
compiler/modules/capped_replica_bitcell_array.py
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@ -33,22 +33,18 @@ class capped_replica_bitcell_array(bitcell_base_array):
self.column_size = cols self.column_size = cols
self.row_size = rows self.row_size = rows
# This is how many RBLs are in all the arrays # This is how many RBLs are in all the arrays
if rbl: self.rbl = rbl
self.rbl = rbl # This specifies which RBL to put on the left or right by port number
else:
self.rbl=[1, 1 if len(self.all_ports)>1 else 0]
# This specifies which RBL to put on the left or right
# by port number
# This could be an empty list # This could be an empty list
if left_rbl is not None: if left_rbl is not None:
self.left_rbl = left_rbl self.left_rbl = left_rbl
else: else:
self.left_rbl = [0] self.left_rbl = []
# This could be an empty list # This could be an empty list
if right_rbl is not None: if right_rbl is not None:
self.right_rbl = right_rbl self.right_rbl = right_rbl
else: else:
self.right_rbl=[1] if len(self.all_ports) > 1 else [] self.right_rbl=[]
self.rbls = self.left_rbl + self.right_rbl self.rbls = self.left_rbl + self.right_rbl
# Two dummy rows plus replica even if we don't add the column # Two dummy rows plus replica even if we don't add the column

3
compiler/modules/replica_bitcell_array.py
View File

@ -37,8 +37,7 @@ class replica_bitcell_array(bitcell_base_array):
self.row_size = rows self.row_size = rows
# This is how many RBLs are in all the arrays # This is how many RBLs are in all the arrays
self.rbl = rbl self.rbl = rbl
# This specifies which RBL to put on the left or right # This specifies which RBL to put on the left or right by port number
# by port number
# This could be an empty list # This could be an empty list
if left_rbl is not None: if left_rbl is not None:
self.left_rbl = left_rbl self.left_rbl = left_rbl