Pin generation instead of parsing

This commit is contained in:
Bugra Onal 2022-08-18 21:09:48 -07:00
parent eceb35f205
commit d3753556c1
3 changed files with 42 additions and 20 deletions

View File

@ -48,7 +48,6 @@ class fake_sram(sram_config):
self.words_per_row = words_per_row self.words_per_row = words_per_row
self.compute_sizes() self.compute_sizes()
self.pins = ['vdd', 'gnd', 'clk0'] # TODO: remove clk
def setup_multiport_constants(self): def setup_multiport_constants(self):
""" """
@ -91,13 +90,6 @@ class fake_sram(sram_config):
self.readonly_ports.append(port_number) self.readonly_ports.append(port_number)
port_number += 1 port_number += 1
def str_to_pins(self, s):
pinsRE = re.compile(r'^(\w+)\[(\d+):(\d+)\]')
match = pinsRE.match(s)
port, start, end = match.group(1, 2, 3)
pins = [port + '[' + str(p) + ']' for p in range(int(start) - int(end) + 1)]
return pins
def parse_html(self, filename): def parse_html(self, filename):
""" """
Parse the HTML file generated from previous SRAM generation Parse the HTML file generated from previous SRAM generation
@ -124,15 +116,42 @@ class fake_sram(sram_config):
elif val.group(1) == 'Area (&microm<sup>2</sup>)': elif val.group(1) == 'Area (&microm<sup>2</sup>)':
self.height = int(val.group(2) ** 0.5) self.height = int(val.group(2) ** 0.5)
self.width = int(val.group(2) ** 0.5) self.width = int(val.group(2) ** 0.5)
if 'Timing Data' in line: self.compute_sizes()
timingRE = re.compile(r'<tr><td>([\w\[\]:]*) \w* \w*</td><td>[\w\.]*</td><td>[\w\.]*</td><td>\w*</td></tr>')
values = timingRE.finditer(line) def generate_pins(self):
for val in values: self.pins = ['vdd', 'gnd']
if '[' in val.group(1): self.pins.extend(['clk{}'.format(port) for port in range(
pins = self.str_to_pins(val.group(1)) self.num_rw_ports + self.num_r_ports + self.num_w_ports)])
for pin in pins: for port in range(self.num_rw_ports):
if pin not in self.pins: self.pins.extend(['din{0}[{1}]]'.format(port, bit)
self.pins.append(pin) for bit in range(self.num_cols)])
else: self.pins.extend(['dout{0}[{1}]]'.format(port, bit)
if val.group(1) not in self.pins: for bit in range(self.num_cols)])
self.pins.append(val.group(1)) self.pins.extend(['addr{0}[{1}]]'.format(port, bit)
for bit in range(self.addr_size)])
if self.num_wmasks != 0:
self.pins.extend(['wmask{0}[{1}]]'.format(port, bit)
for bit in range(self.num_wmasks)])
self.pins.extend(['csb{}'.format(port), 'web{}'.format(port)])
start_port = self.num_rw_ports
for port in range(start_port, start_port + self.num_r_ports):
self.pins.extend(['dout{0}[{1}]]'.format(port, bit)
for bit in range(self.num_cols)])
self.pins.extend(['addr{0}[{1}]]'.format(port, bit)
for bit in range(self.addr_size)])
self.pins.extend(['csb{}'.format(port)])
start_port += self.num_r_ports
for port in range(start_port, start_port + self.num_w_ports):
self.pins.extend(['din{0}[{1}]]'.format(port, bit)
for bit in range(self.num_cols)])
self.pins.extend(['addr{0}[{1}]]'.format(port, bit)
for bit in range(self.addr_size)])
if self.num_wmasks != 0:
self.pins.extend(['wmask{0}[{1}]]'.format(port, bit)
for bit in range(self.num_wmasks)])
self.pins.extend(['csb{}'.format(port), 'web{}'.format(port)])

View File

@ -50,6 +50,7 @@ s = fake_sram(name=OPTS.output_name,
num_spare_cols=OPTS.num_spare_cols) num_spare_cols=OPTS.num_spare_cols)
s.parse_html(args[1]) s.parse_html(args[1])
s.generate_pins()
s.setup_multiport_constants() s.setup_multiport_constants()
OPTS.netlist_only = True OPTS.netlist_only = True

View File

@ -123,6 +123,8 @@ class options(optparse.Values):
################### ###################
# Tool options # Tool options
################### ###################
# Top process that was ran (openram, memchar, memfunc)
top_process = None
# Variable to select the variant of spice # Variable to select the variant of spice
spice_name = None spice_name = None
# The spice executable being used which is derived from the user PATH. # The spice executable being used which is derived from the user PATH.