mirror of https://github.com/VLSIDA/OpenRAM.git
New control logic, netlist only working
This commit is contained in:
Matt Guthaus
parent
275891084b
commit
d36f14b408
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@ -82,7 +82,7 @@ class bank(design.design):
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for port in self.read_ports:
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for bit in range(self.word_size):
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self.add_pin("dout{0}_{1}".format(port,bit),"OUTPUT")
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for port in self.read_ports:
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for port in self.all_ports:
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self.add_pin(self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port]),"OUTPUT")
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for port in self.write_ports:
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for bit in range(self.word_size):
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@ -128,14 +128,13 @@ class bank(design.design):
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def route_rbl(self,port):
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""" Route the rbl_bl and rbl_wl """
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if self.port_data[port].has_rbl():
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bl_pin_name = self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port])
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bl_pin = self.bitcell_array_inst.get_pin(bl_pin_name)
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self.add_layout_pin(text="rbl_bl{0}".format(port),
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layer=bl_pin.layer,
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offset=bl_pin.ll(),
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height=bl_pin.height(),
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width=bl_pin.width())
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bl_pin_name = self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port])
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bl_pin = self.bitcell_array_inst.get_pin(bl_pin_name)
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self.add_layout_pin(text="rbl_bl{0}".format(port),
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layer=bl_pin.layer,
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offset=bl_pin.ll(),
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height=bl_pin.height(),
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width=bl_pin.width())
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@ -202,10 +201,7 @@ class bank(design.design):
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# LOWER RIGHT QUADRANT
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# Below the bitcell array
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if self.port_data[port].has_rbl():
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self.port_data_offsets[port] = vector(self.main_bitcell_array_left - self.bitcell_array.cell.width,0)
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else:
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self.port_data_offsets[port] = vector(self.main_bitcell_array_left,0)
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self.port_data_offsets[port] = vector(self.main_bitcell_array_left - self.bitcell_array.cell.width,0)
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# UPPER LEFT QUADRANT
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# To the left of the bitcell array
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@ -364,36 +360,15 @@ class bank(design.design):
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self.add_mod(self.port_address)
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# The number of replica lines depends on the port configuration
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rbl_counts = [self.read_ports.count(p) for p in self.all_ports]
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self.num_rbl = sum(rbl_counts)
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# The replica array indices always start at 0, so this will map them to
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# the correct SRAM port
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# (e.g. if port 0 is w, then port 1 will use RBL 0 in replica bitcell array
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# because write ports don't use an RBL)
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self.port_rbl_map = {}
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index = 0
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for (i,num) in enumerate(rbl_counts):
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if num>0:
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self.port_rbl_map[i]=index
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index += 1
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if len(rbl_counts)<2:
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rbl_counts.append(0)
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# Which bitcell port should be used in the RBL
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# For now (since only 2 ports), if port 0 is not a read port, skip it in the RBLs
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bitcell_ports=list(range(len(self.read_ports)))
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if 0 not in self.read_ports:
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bitcell_ports = [x+1 for x in bitcell_ports]
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self.port_rbl_map = self.all_ports
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self.num_rbl = len(self.all_ports)
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self.bitcell_array = factory.create(module_type="replica_bitcell_array",
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cols=self.num_cols,
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rows=self.num_rows,
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left_rbl=rbl_counts[0],
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right_rbl=rbl_counts[1],
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bitcell_ports=bitcell_ports)
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left_rbl=1,
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right_rbl=1 if len(self.all_ports)>1 else 0,
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bitcell_ports=self.all_ports)
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self.add_mod(self.bitcell_array)
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@ -421,8 +396,7 @@ class bank(design.design):
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for wordline in self.wl_names:
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temp.append("{0}_{1}".format(wordline,row))
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for port in self.all_ports:
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if self.port_data[port].has_rbl():
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temp.append("wl_en{0}".format(port))
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temp.append("wl_en{0}".format(port))
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temp.append("vdd")
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temp.append("gnd")
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self.connect_inst(temp)
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@ -442,11 +416,10 @@ class bank(design.design):
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mod=self.port_data[port])
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temp = []
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if self.port_data[port].has_rbl():
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rbl_bl_name=self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port])
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rbl_br_name=self.bitcell_array.get_rbl_br_name(self.port_rbl_map[port])
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temp.append(rbl_bl_name)
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temp.append(rbl_br_name)
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rbl_bl_name=self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port])
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rbl_br_name=self.bitcell_array.get_rbl_br_name(self.port_rbl_map[port])
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temp.append(rbl_bl_name)
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temp.append(rbl_br_name)
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for col in range(self.num_cols):
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temp.append("{0}_{1}".format(self.bl_names[port],col))
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temp.append("{0}_{1}".format(self.br_names[port],col))
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@ -710,11 +683,10 @@ class bank(design.design):
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inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name)
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# Connect the replica bitlines
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if self.port_data[port].has_rbl():
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rbl_bl_name=self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port])
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rbl_br_name=self.bitcell_array.get_rbl_br_name(self.port_rbl_map[port])
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self.connect_bitline(inst1, inst2, rbl_bl_name, "rbl_bl")
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self.connect_bitline(inst1, inst2, rbl_br_name, "rbl_br")
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rbl_bl_name=self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port])
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rbl_br_name=self.bitcell_array.get_rbl_br_name(self.port_rbl_map[port])
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self.connect_bitline(inst1, inst2, rbl_bl_name, "rbl_bl")
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self.connect_bitline(inst1, inst2, rbl_br_name, "rbl_br")
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@ -125,10 +125,10 @@ class control_logic(design.design):
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self.add_mod(self.wl_en_driver)
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# w_en drives every write driver
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self.wen_and2 = factory.create(module_type="pand2",
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self.wen_and = factory.create(module_type="pand3",
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size=self.word_size+8,
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height=dff_height)
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self.add_mod(self.wen_and2)
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self.add_mod(self.wen_and)
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# s_en drives every sense amp
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self.sen_and2 = factory.create(module_type="pand2",
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@ -147,11 +147,13 @@ class control_logic(design.design):
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# prepended 3 inverter stages to guarantee it is slower and odd polarity
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self.p_en_bar_driver = factory.create(module_type="pdriver",
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fanout=self.num_cols,
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neg_polarity=True,
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height=dff_height)
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self.add_mod(self.p_en_bar_driver)
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self.nand2 = factory.create(module_type="pnand2",
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height=dff_height)
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self.add_mod(self.nand2)
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# if (self.port_type == "rw") or (self.port_type == "r"):
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# from importlib import reload
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@ -330,12 +332,9 @@ class control_logic(design.design):
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if self.port_type == "rw":
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self.input_list = ["csb", "web"]
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self.rbl_list = ["rbl_bl"]
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elif self.port_type == "r":
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self.input_list = ["csb"]
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self.rbl_list = ["rbl_bl"]
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else:
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self.input_list = ["csb"]
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self.rbl_list = []
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self.rbl_list = ["rbl_bl"]
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if self.port_type == "rw":
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self.dff_output_list = ["cs_bar", "cs", "we_bar", "we"]
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@ -385,7 +384,7 @@ class control_logic(design.design):
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self.create_wen_row()
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.create_sen_row()
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self.create_delay()
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self.create_delay()
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self.create_pen_row()
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@ -422,9 +421,9 @@ class control_logic(design.design):
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.place_sen_row(row)
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row += 1
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self.place_delay(row)
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height = self.delay_inst.uy()
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control_center_y = self.delay_inst.by()
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self.place_delay(row)
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height = self.delay_inst.uy()
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control_center_y = self.delay_inst.by()
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# This offset is used for placement of the control logic in the SRAM level.
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self.control_logic_center = vector(self.ctrl_dff_inst.rx(), control_center_y)
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@ -446,6 +445,7 @@ class control_logic(design.design):
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self.route_wen()
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.route_sen()
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self.route_delay()
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self.route_pen()
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self.route_clk_buf()
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self.route_gated_clk_bar()
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@ -457,7 +457,7 @@ class control_logic(design.design):
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""" Create the replica bitline """
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self.delay_inst=self.add_inst(name="delay_chain",
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mod=self.delay_chain)
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self.connect_inst(["rbl_bl", "pre_s_en", "vdd", "gnd"])
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self.connect_inst(["rbl_bl", "rbl_bl_delay", "vdd", "gnd"])
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def place_delay(self,row):
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""" Place the replica bitline """
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@ -468,6 +468,11 @@ class control_logic(design.design):
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offset = vector(self.delay_chain.width, y_off)
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self.delay_inst.place(offset, mirror="MY")
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def route_delay(self):
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# Input from RBL goes to the delay line for futher delay
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self.copy_layout_pin(self.delay_inst, "in", "rbl_bl")
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def create_clk_buf_row(self):
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""" Create the multistage and gated clock buffer """
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@ -604,10 +609,14 @@ class control_logic(design.design):
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self.connect_output(self.wl_en_inst, "Z", "wl_en")
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def create_pen_row(self):
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# input: gated_clk_bar, output: p_en_bar
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self.p_en_bar_inst=self.add_inst(name="inv_p_en_bar",
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self.p_en_bar_inst=self.add_inst(name="nand_p_en_bar",
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mod=self.nand2)
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self.connect_inst(["gated_clk_buf", "rbl_bl_delay", "p_en_bar_unbuf", "vdd", "gnd"])
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self.p_en_bar_inst=self.add_inst(name="buf_p_en_bar",
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mod=self.p_en_bar_driver)
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self.connect_inst(["gated_clk_buf", "p_en_bar", "vdd", "gnd"])
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self.connect_inst(["p_en_bar_unbuf", "p_en_bar", "vdd", "gnd"])
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def place_pen_row(self,row):
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@ -633,7 +642,7 @@ class control_logic(design.design):
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# GATE FOR S_EN
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self.s_en_gate_inst = self.add_inst(name="buf_s_en_and",
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mod=self.sen_and2)
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self.connect_inst(["pre_s_en", input_name, "s_en", "vdd", "gnd"])
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self.connect_inst(["rbl_bl_delay", input_name, "s_en", "vdd", "gnd"])
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def place_sen_row(self,row):
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@ -667,12 +676,13 @@ class control_logic(design.design):
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self.connect_output(self.s_en_gate_inst, "Z", "s_en")
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# Input from RBL goes to the delay line for futher delay
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self.copy_layout_pin(self.delay_inst, "in", "rbl_bl")
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def create_wen_row(self):
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self.rbl_bl_delay_inv_inst = self.add_inst(name="rbl_bl_delay_inv",
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mod=self.inv)
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self.connect_inst(["rbl_bl_delay", "rbl_bl_delay_bar", "vdd", "gnd"])
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# input: we (or cs) output: w_en
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if self.port_type == "rw":
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input_name = "we"
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@ -682,8 +692,8 @@ class control_logic(design.design):
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# GATE THE W_EN
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self.w_en_gate_inst = self.add_inst(name="w_en_and",
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mod=self.wen_and2)
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self.connect_inst([input_name, "gated_clk_bar", "w_en", "vdd", "gnd"])
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mod=self.wen_and)
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self.connect_inst([input_name, "rbl_bl_delay_bar", "gated_clk_bar", "w_en", "vdd", "gnd"])
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def place_wen_row(self,row):
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@ -82,9 +82,8 @@ class port_data(design.design):
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def add_pins(self):
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""" Adding pins for port address module"""
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if self.has_rbl():
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self.add_pin("rbl_bl","INOUT")
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self.add_pin("rbl_br","INOUT")
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self.add_pin("rbl_bl","INOUT")
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self.add_pin("rbl_br","INOUT")
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for bit in range(self.num_cols):
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self.add_pin("{0}_{1}".format(self.bl_names[self.port], bit),"INOUT")
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self.add_pin("{0}_{1}".format(self.br_names[self.port], bit),"INOUT")
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@ -150,30 +149,18 @@ class port_data(design.design):
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def add_modules(self):
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if self.port in self.read_ports:
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# Extra column +1 is for RBL
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# Precharge will be shifted left if needed
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self.precharge_array = factory.create(module_type="precharge_array",
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columns=self.num_cols + 1,
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bitcell_bl=self.bl_names[self.port],
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bitcell_br=self.br_names[self.port])
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self.add_mod(self.precharge_array)
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# Extra column +1 is for RBL
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# Precharge will be shifted left if needed
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self.precharge_array = factory.create(module_type="precharge_array",
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columns=self.num_cols + 1,
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bitcell_bl=self.bl_names[self.port],
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bitcell_br=self.br_names[self.port])
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self.add_mod(self.precharge_array)
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self.sense_amp_array = factory.create(module_type="sense_amp_array",
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word_size=self.word_size,
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words_per_row=self.words_per_row)
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self.add_mod(self.sense_amp_array)
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else:
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# Precharge is needed when we have a column mux or for byte writes
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# to prevent corruption of half-selected cells, so just always add it
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# This is a little power inefficient for write ports without a column mux,
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# but it is simpler.
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self.precharge_array = factory.create(module_type="precharge_array",
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columns=self.num_cols,
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bitcell_bl=self.bl_names[self.port],
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bitcell_br=self.br_names[self.port])
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self.add_mod(self.precharge_array)
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self.sense_amp_array = None
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self.sense_amp_array = factory.create(module_type="sense_amp_array",
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word_size=self.word_size,
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words_per_row=self.words_per_row)
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self.add_mod(self.sense_amp_array)
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if self.col_addr_size > 0:
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@ -238,14 +225,14 @@ class port_data(design.design):
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temp = []
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# Use left BLs for RBL
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if self.has_rbl() and self.port==0:
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if self.port==0:
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temp.append("rbl_bl")
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temp.append("rbl_br")
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for bit in range(self.num_cols):
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temp.append(self.bl_names[self.port]+"_{0}".format(bit))
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temp.append(self.br_names[self.port]+"_{0}".format(bit))
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# Use right BLs for RBL
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if self.has_rbl() and self.port==1:
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if self.port==1:
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temp.append("rbl_bl")
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temp.append("rbl_br")
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temp.extend(["p_en_bar", "vdd"])
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@ -368,7 +355,7 @@ class port_data(design.design):
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vertical_port_order.append(self.write_driver_array_inst)
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# Add one column for the the RBL
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if self.has_rbl() and self.port==0:
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if self.port==0:
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x_offset = self.bitcell.width
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else:
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x_offset = 0
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@ -438,7 +425,7 @@ class port_data(design.design):
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inst1 = self.column_mux_array_inst
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inst2 = self.precharge_array_inst
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if self.has_rbl() and self.port==0:
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if self.port==0:
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self.connect_bitlines(inst1, inst2, self.num_cols, inst2_start_bit=1)
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else:
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self.connect_bitlines(inst1, inst2, self.num_cols)
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@ -460,7 +447,7 @@ class port_data(design.design):
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inst1 = self.precharge_array_inst
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inst1_bl_name = "bl_{}"
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inst1_br_name = "br_{}"
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if self.has_rbl() and self.port==0:
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if self.port==0:
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start_bit=1
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else:
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start_bit=0
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@ -484,7 +471,7 @@ class port_data(design.design):
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inst1 = self.precharge_array_inst
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inst1_bl_name = "bl_{}"
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inst1_br_name = "br_{}"
|
||||
if self.has_rbl() and self.port==0:
|
||||
if self.port==0:
|
||||
start_bit=1
|
||||
else:
|
||||
start_bit=0
|
||||
|
|
@ -507,11 +494,11 @@ class port_data(design.design):
|
|||
""" Add the bitline pins for the given port """
|
||||
|
||||
# Connect one bitline to the RBL and offset the indices for the other BLs
|
||||
if self.has_rbl() and self.port==0:
|
||||
if self.port==0:
|
||||
self.copy_layout_pin(self.precharge_array_inst, "bl_0", "rbl_bl")
|
||||
self.copy_layout_pin(self.precharge_array_inst, "br_0", "rbl_br")
|
||||
bit_offset=1
|
||||
elif self.has_rbl() and self.port==1:
|
||||
elif self.port==1:
|
||||
self.copy_layout_pin(self.precharge_array_inst, "bl_{}".format(self.num_cols), "rbl_bl")
|
||||
self.copy_layout_pin(self.precharge_array_inst, "br_{}".format(self.num_cols), "rbl_br")
|
||||
bit_offset=0
|
||||
|
|
@ -603,5 +590,3 @@ class port_data(design.design):
|
|||
if self.precharge_array_inst:
|
||||
self.graph_inst_exclude.add(self.precharge_array_inst)
|
||||
|
||||
def has_rbl(self):
|
||||
return self.port in self.read_ports
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ class replica_bitcell_array(design.design):
|
|||
self.right_rbl = right_rbl
|
||||
self.bitcell_ports = bitcell_ports
|
||||
|
||||
debug.check(left_rbl+right_rbl==len(self.read_ports),"Invalid number of RBLs for port configuration.")
|
||||
debug.check(left_rbl+right_rbl==len(self.all_ports),"Invalid number of RBLs for port configuration.")
|
||||
debug.check(left_rbl+right_rbl==len(self.bitcell_ports),"Bitcell ports must match total RBLs.")
|
||||
|
||||
# Two dummy rows/cols plus replica for each port
|
||||
|
|
|
|||
|
|
@ -339,7 +339,7 @@ class sram_base(design, verilog, lef):
|
|||
for port in self.read_ports:
|
||||
for bit in range(self.word_size):
|
||||
temp.append("DOUT{0}[{1}]".format(port,bit))
|
||||
for port in self.read_ports:
|
||||
for port in self.all_ports:
|
||||
temp.append("rbl_bl{0}".format(port))
|
||||
for port in self.write_ports:
|
||||
for bit in range(self.word_size):
|
||||
|
|
@ -499,9 +499,7 @@ class sram_base(design, verilog, lef):
|
|||
if port in self.readwrite_ports:
|
||||
temp.append("web{}".format(port))
|
||||
temp.append("clk{}".format(port))
|
||||
|
||||
if port in self.read_ports:
|
||||
temp.append("rbl_bl{}".format(port))
|
||||
temp.append("rbl_bl{}".format(port))
|
||||
|
||||
# Ouputs
|
||||
if port in self.read_ports:
|
||||
|
|
|
|||
Loading…
Reference in New Issue