New control logic, netlist only working

compiler/sram/sram_base.py

@@ -339,7 +339,7 @@ class sram_base(design, verilog, lef):
         for port in self.read_ports:
             for bit in range(self.word_size):
                 temp.append("DOUT{0}[{1}]".format(port,bit))
-        for port in self.read_ports:
+        for port in self.all_ports:
             temp.append("rbl_bl{0}".format(port))
         for port in self.write_ports:
             for bit in range(self.word_size):
@@ -499,9 +499,7 @@ class sram_base(design, verilog, lef):
             if port in self.readwrite_ports:
                 temp.append("web{}".format(port))
             temp.append("clk{}".format(port))
-
-            if port in self.read_ports:
-                temp.append("rbl_bl{}".format(port))
+            temp.append("rbl_bl{}".format(port))
 
             # Ouputs
             if port in self.read_ports: