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New control logic, netlist only working

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This commit is contained in:
Matt Guthaus
2019-08-07 17:14:33 -07:00
parent 275891084b
commit d36f14b408
5 changed files with 82 additions and 117 deletions
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compiler/modules/replica_bitcell_array.py
+1 -1
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@@ -35,7 +35,7 @@ class replica_bitcell_array(design.design):
self.right_rbl = right_rbl
self.bitcell_ports = bitcell_ports
debug.check(left_rbl+right_rbl==len(self.read_ports),"Invalid number of RBLs for port configuration.")
debug.check(left_rbl+right_rbl==len(self.all_ports),"Invalid number of RBLs for port configuration.")
debug.check(left_rbl+right_rbl==len(self.bitcell_ports),"Bitcell ports must match total RBLs.")
# Two dummy rows/cols plus replica for each port