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Merge branch 'pdriver' into dev

This commit is contained in:
Jennifer Eve Sowash 2018-12-07 14:37:25 -08:00
parent 5248482fab a6eec10f41
commit d302f1cd0a
1 changed files with 12 additions and 12 deletions
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24
compiler/pgates/pdriver.py
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@ -9,12 +9,9 @@ from pinv import pinv
class pdriver(pgate.pgate): class pdriver(pgate.pgate):
""" """
This instantiates an even or odd number of inverters sized for driving a load. This instantiates an even or odd number of inverters sized for driving a load.
""" """
unique_id = 1 unique_id = 1
inv_list = []
inv_inst_list = []
calc_size_list = []
def __init__(self, height=None, name="", neg_polarity=False, c_load=8, size_list = []): def __init__(self, height=None, name="", neg_polarity=False, c_load=8, size_list = []):
@ -48,26 +45,24 @@ class pdriver(pgate.pgate):
self.num_inv = len(self.size_list) self.num_inv = len(self.size_list)
else: else:
# find the number of stages # find the number of stages
c_prev = int(round(self.c_load/self.stage_effort)) #c_load is a unit inverter fanout, not a capacitance so c_in=1
num_stages = 1 num_stages = int(round(log(self.c_load)/log(4)))
while c_prev > 1: #stop when the first stage is 1
c_prev = int(round(c_prev/self.stage_effort))
num_stages+=1
# find inv_num and compute sizes # find inv_num and compute sizes
if self.neg_polarity: if self.neg_polarity:
if (num_stages % 2 == 0): # if num_stages is even if (num_stages % 2 == 0): # if num_stages is even
self.diff_polarity(num_stages=num_stages) self.diff_polarity(num_stages=num_stages)
else: # if num_stages is odd else: # if num_stages is odd
self.same_polarity(num_stages=num_stages) self.same_polarity(num_stages=num_stages)
else: # positive polarity else: # positive polarity
if (num_stages % 2 == 0): if (num_stages % 2 == 0):
self.same_polarity(num_stages=num_stages) self.same_polarity(num_stages=num_stages)
else: else:
self.diff_polarity(num_stages=num_stages) self.diff_polarity(num_stages=num_stages)
def same_polarity(self, num_stages): def same_polarity(self, num_stages):
self.calc_size_list = []
self.num_inv = num_stages self.num_inv = num_stages
# compute sizes # compute sizes
c_prev = self.c_load c_prev = self.c_load
@ -77,6 +72,7 @@ class pdriver(pgate.pgate):
def diff_polarity(self, num_stages): def diff_polarity(self, num_stages):
self.calc_size_list = []
# find which delay is smaller # find which delay is smaller
delay_below = ((num_stages-1)*(self.c_load**(1/num_stages-1))) + num_stages-1 delay_below = ((num_stages-1)*(self.c_load**(1/num_stages-1))) + num_stages-1
delay_above = ((num_stages+1)*(self.c_load**(1/num_stages+1))) + num_stages+1 delay_above = ((num_stages+1)*(self.c_load**(1/num_stages+1))) + num_stages+1
@ -96,6 +92,8 @@ class pdriver(pgate.pgate):
def create_netlist(self): def create_netlist(self):
inv_list = []
self.add_pins() self.add_pins()
self.add_modules() self.add_modules()
self.create_insts() self.create_insts()
@ -116,7 +114,8 @@ class pdriver(pgate.pgate):
self.add_pin("vdd") self.add_pin("vdd")
self.add_pin("gnd") self.add_pin("gnd")
def add_modules(self): def add_modules(self):
self.inv_list = []
if len(self.size_list) > 0: # size list specified if len(self.size_list) > 0: # size list specified
for x in range(len(self.size_list)): for x in range(len(self.size_list)):
self.inv_list.append(pinv(size=self.size_list[x], height=self.row_height)) self.inv_list.append(pinv(size=self.size_list[x], height=self.row_height))
@ -128,6 +127,7 @@ class pdriver(pgate.pgate):
def create_insts(self): def create_insts(self):
self.inv_inst_list = []
for x in range(1,self.num_inv+1): for x in range(1,self.num_inv+1):
# Create first inverter # Create first inverter
if x == 1: if x == 1: