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SRAM single bank passing DRC/LVS.

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This commit is contained in:
Matt Guthaus
2017-09-13 15:46:41 -07:00
parent 3ea003c367
commit d29dd03373
16 changed files with 561 additions and 805 deletions
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compiler/tests/19_four_bank_test.py → compiler/tests/19_multi_bank_test.py
+5 -5
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@@ -15,7 +15,7 @@ OPTS = globals.get_opts()
class bank_test(unittest.TestCase):
class multi_bank_test(unittest.TestCase):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
@@ -25,20 +25,20 @@ class bank_test(unittest.TestCase):
import bank
debug.info(1, "No column mux")
a = bank.bank(word_size=4, num_words=16, words_per_row=1, num_banks=4, name="test_sram1")
a = bank.bank(word_size=4, num_words=16, words_per_row=1, num_banks=2, name="test_bank1")
self.local_check(a)
debug.info(1, "Two way column mux")
a = bank.bank(word_size=4, num_words=32, words_per_row=2, num_banks=4, name="test_sram2")
a = bank.bank(word_size=4, num_words=32, words_per_row=2, num_banks=2, name="test_bank2")
self.local_check(a)
debug.info(1, "Four way column mux")
a = bank.bank(word_size=4, num_words=64, words_per_row=4, num_banks=4, name="test_sram3")
a = bank.bank(word_size=4, num_words=64, words_per_row=4, num_banks=2, name="test_bank3")
self.local_check(a)
# Eight way has a short circuit of one column mux select to gnd rail
# debug.info(1, "Eight way column mux")
# a = bank.bank(word_size=2, num_words=128, words_per_row=8, num_banks=2, name="test_sram4")
# a = bank.bank(word_size=2, num_words=128, words_per_row=8, num_banks=2, name="test_bank4")
# self.local_check(a)
OPTS.check_lvsdrc = True
compiler/tests/19_single_bank_test.py
+5 -5
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@@ -16,7 +16,7 @@ OPTS = globals.get_opts()
#@unittest.skip("SKIPPING 20_sram_test")
class bank_test(unittest.TestCase):
class single_bank_test(unittest.TestCase):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
@@ -26,20 +26,20 @@ class bank_test(unittest.TestCase):
import bank
debug.info(1, "No column mux")
a = bank.bank(word_size=4, num_words=16, words_per_row=1, num_banks=1, name="test_sram1")
a = bank.bank(word_size=4, num_words=16, words_per_row=1, num_banks=1, name="test_bank1")
self.local_check(a)
debug.info(1, "Two way column mux")
a = bank.bank(word_size=4, num_words=32, words_per_row=2, num_banks=1, name="test_sram2")
a = bank.bank(word_size=4, num_words=32, words_per_row=2, num_banks=1, name="test_bank2")
self.local_check(a)
debug.info(1, "Four way column mux")
a = bank.bank(word_size=4, num_words=64, words_per_row=4, num_banks=1, name="test_sram3")
a = bank.bank(word_size=4, num_words=64, words_per_row=4, num_banks=1, name="test_bank3")
self.local_check(a)
# Eight way has a short circuit of one column mux select to gnd rail
# debug.info(1, "Eight way column mux")
# a = bank.bank(word_size=2, num_words=128, words_per_row=8, num_banks=1, name="test_sram4")
# a = bank.bank(word_size=2, num_words=128, words_per_row=8, num_banks=1, name="test_bank4")
# self.local_check(a)
OPTS.check_lvsdrc = True
compiler/tests/19_two_bank_test.py
-69
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@@ -1,69 +0,0 @@
#!/usr/bin/env python2.7
"""
Run a regresion test on various srams
"""
import unittest
from testutils import header
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
import debug
import calibre
OPTS = globals.get_opts()
class bank_test(unittest.TestCase):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
import bank
debug.info(1, "No column mux")
a = bank.bank(word_size=4, num_words=16, words_per_row=1, num_banks=2, name="test_sram1")
self.local_check(a)
debug.info(1, "Two way column mux")
a = bank.bank(word_size=4, num_words=32, words_per_row=2, num_banks=2, name="test_sram2")
self.local_check(a)
debug.info(1, "Four way column mux")
a = bank.bank(word_size=4, num_words=64, words_per_row=4, num_banks=2, name="test_sram3")
self.local_check(a)
# Eight way has a short circuit of one column mux select to gnd rail
# debug.info(1, "Eight way column mux")
# a = bank.bank(word_size=2, num_words=128, words_per_row=8, num_banks=2, name="test_sram4")
# self.local_check(a)
OPTS.check_lvsdrc = True
globals.end_openram()
def local_check(self, a):
tempspice = OPTS.openram_temp + "temp.sp"
tempgds = OPTS.openram_temp + "temp.gds"
a.sp_write(tempspice)
a.gds_write(tempgds)
self.assertFalse(calibre.run_drc(a.name, tempgds))
self.assertFalse(calibre.run_lvs(a.name, tempgds, tempspice))
os.remove(tempspice)
os.remove(tempgds)
# reset the static duplicate name checker for unit tests
import design
design.design.name_map=[]
# instantiate a copy of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()
compiler/tests/20_sram_1bank_test.py
+14 -2
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@@ -25,10 +25,22 @@ class sram_1bank_test(unittest.TestCase):
import sram
debug.info(1, "Testing sample 8bit, 64word SRAM, 1 bank")
a = sram.sram(word_size=8, num_words=128, num_banks=1, name="test_sram1")
debug.info(1, "Single bank, no column mux with control logic")
a = sram.sram(word_size=4, num_words=16, num_banks=1, name="test_sram1")
self.local_check(a)
debug.info(1, "Single bank two way column mux with control logic")
a = sram.sram(word_size=4, num_words=32, num_banks=1, name="test_sram2")
self.local_check(a)
debug.info(1, "Single bank, four way column mux with control logic")
a = sram.sram(word_size=4, num_words=64, num_banks=1, name="test_sram3")
self.local_check(a)
# debug.info(1, "Single bank, eight way column mux with control logic")
# a = sram.sram(word_size=2, num_words=128, num_banks=1, name="test_sram4")
# self.local_check(a)
OPTS.check_lvsdrc = True
globals.end_openram()
compiler/tests/20_sram_2bank_test.py
+14 -2
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@@ -25,10 +25,22 @@ class sram_2bank_test(unittest.TestCase):
import sram
debug.info(1, "Testing sample 8bit, 128word SRAM, 2 banks")
a = sram.sram(word_size=8, num_words=128, num_banks=2, name="test_sram1")
debug.info(1, "Two bank, no column mux with control logic")
a = sram.sram(word_size=4, num_words=32, num_banks=2, name="test_sram1")
self.local_check(a)
debug.info(1, "Two bank two way column mux with control logic")
a = sram.sram(word_size=4, num_words=64, num_banks=2, name="test_sram2")
self.local_check(a)
debug.info(1, "Two bank, four way column mux with control logic")
a = sram.sram(word_size=4, num_words=128, num_banks=2, name="test_sram3")
self.local_check(a)
# debug.info(1, "Two bank, eight way column mux with control logic")
# a = sram.sram(word_size=2, num_words=256 num_banks=2, name="test_sram4")
# self.local_check(a)
OPTS.check_lvsdrc = True
globals.end_openram()
compiler/tests/20_sram_4bank_test.py
+14 -2
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@@ -25,10 +25,22 @@ class sram_4bank_test(unittest.TestCase):
import sram
debug.info(1, "Testing sample 8bit, 128word SRAM, 4 banks")
a = sram.sram(word_size=8, num_words=128, num_banks=4, name="test_sram1")
debug.info(1, "Four bank, no column mux with control logic")
a = sram.sram(word_size=4, num_words=32, num_banks=4, name="test_sram1")
self.local_check(a)
debug.info(1, "Four bank two way column mux with control logic")
a = sram.sram(word_size=4, num_words=64, num_banks=4, name="test_sram2")
self.local_check(a)
debug.info(1, "Four bank, four way column mux with control logic")
a = sram.sram(word_size=4, num_words=128, num_banks=4, name="test_sram3")
self.local_check(a)
# debug.info(1, "Four bank, eight way column mux with control logic")
# a = sram.sram(word_size=2, num_words=256, num_banks=4, name="test_sram4")
# self.local_check(a)
OPTS.check_lvsdrc = True
globals.end_openram()