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placement positions problem fixed, incorrect w,h calculations were the problem

This commit is contained in:
samuelkcrow 2022-12-10 19:03:55 -08:00
parent 68fb4e3c63
commit d224c06b25
2 changed files with 16 additions and 15 deletions
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8
compiler/modules/capped_bitcell_array.py
View File

@ -219,7 +219,7 @@ class capped_bitcell_array(bitcell_base_array):
self.row_end_offset = vector(self.cell.width, self.cell.height) self.row_end_offset = vector(self.cell.width, self.cell.height)
# Everything is computed with the replica array # Everything is computed with the replica array
self.replica_bitcell_array_inst.place(offset=self.bitcell_offset.scale(-1, -1)) # may need to depend on rbl self.replica_bitcell_array_inst.place(offset=0)
self.add_end_caps() self.add_end_caps()
@ -282,7 +282,7 @@ class capped_bitcell_array(bitcell_base_array):
# Far top dummy row (first row above array is NOT flipped if even number of rows) # Far top dummy row (first row above array is NOT flipped if even number of rows)
flip_dummy = (self.row_size + self.rbl[1]) % 2 flip_dummy = (self.row_size + self.rbl[1]) % 2
dummy_row_offset = self.bitcell_offset.scale(1, self.rbl[1] + flip_dummy) + self.replica_bitcell_array_inst.ul() + vector(0, -0.8) dummy_row_offset = self.bitcell_offset.scale(0, self.rbl[1] - 1 + flip_dummy) + self.replica_bitcell_array_inst.ul()
self.dummy_row_insts[1].place(offset=dummy_row_offset, self.dummy_row_insts[1].place(offset=dummy_row_offset,
mirror="MX" if flip_dummy else "R0") mirror="MX" if flip_dummy else "R0")
@ -298,11 +298,11 @@ class capped_bitcell_array(bitcell_base_array):
# Far right dummy col # Far right dummy col
# Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array # Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
dummy_col_offset = self.bitcell_offset.scale(len(self.right_rbl), -self.rbl[0] + 1) + self.replica_bitcell_array_inst.lr() dummy_col_offset = self.bitcell_offset.scale(len(self.right_rbl) - 1, -self.rbl[0]) + self.replica_bitcell_array_inst.lr()
self.dummy_col_insts[1].place(offset=dummy_col_offset) self.dummy_col_insts[1].place(offset=dummy_col_offset)
def copy_layout_pins(self): def copy_layout_pins(self):
for pin_name in self.replica_bitcell_array.get_layout_pins(): for pin_name in self.replica_bitcell_array_inst.get_pins():
if pin_name in ["vdd", "gnd"]: if pin_name in ["vdd", "gnd"]:
continue continue
self.copy_layout_pin(self.replica_bitcell_array_inst, pin_name) self.copy_layout_pin(self.replica_bitcell_array_inst, pin_name)

23
compiler/modules/replica_bitcell_array.py
View File

@ -250,18 +250,18 @@ class replica_bitcell_array(bitcell_base_array):
# Array was at (0, 0) but move everything so it is at the lower left # Array was at (0, 0) but move everything so it is at the lower left
# We move DOWN the number of left RBL even if we didn't add the column to this bitcell array # We move DOWN the number of left RBL even if we didn't add the column to this bitcell array
# Note that this doesn't include the row/col cap # Note that this doesn't include the row/col cap
array_offset = self.bitcell_offset.scale(1 + len(self.left_rbl), 1 + self.rbl[0]) array_offset = self.bitcell_offset.scale(len(self.left_rbl), self.rbl[0])
self.translate_all(array_offset.scale(-1, -1)) self.translate_all(array_offset.scale(-1, -1))
self.width = self.dummy_col_insts[1].rx() + self.unused_offset.x
self.height = self.dummy_row_insts[1].uy()
self.add_layout_pins() self.add_layout_pins()
self.route_supplies() self.route_supplies()
lower_left = self.find_lowest_coords() self.width = (len(self.rbls) + self.column_size) * self.cell.width
upper_right = self.find_highest_coords() self.height = (len(self.rbls) + self.row_size) * self.cell.height
self.width = upper_right.x - lower_left.x
self.height = upper_right.y - lower_left.y
# self.translate_all(lower_left)
self.add_boundary() self.add_boundary()
@ -335,13 +335,13 @@ class replica_bitcell_array(bitcell_base_array):
""" Add the layout pins """ """ Add the layout pins """
# All wordlines # All wordlines
# Main array wl and bl/br # Main array wl
for pin_name in self.all_bitcell_wordline_names: for pin_name in self.all_bitcell_wordline_names:
pin_list = self.bitcell_array_inst.get_pins(pin_name) pin_list = self.bitcell_array_inst.get_pins(pin_name)
for pin in pin_list: for pin in pin_list:
self.add_layout_pin(text=pin_name, self.add_layout_pin(text=pin_name,
layer=pin.layer, layer=pin.layer,
offset=pin.ll(), offset=pin.ll().scale(0, 1),
width=self.width, width=self.width,
height=pin.height()) height=pin.height())
@ -352,16 +352,17 @@ class replica_bitcell_array(bitcell_base_array):
pin = inst.get_pin(pin_name) pin = inst.get_pin(pin_name)
self.add_layout_pin(text=wl_name, self.add_layout_pin(text=wl_name,
layer=pin.layer, layer=pin.layer,
offset=pin.ll(), offset=pin.ll().scale(0, 1),
width=self.width, width=self.width,
height=pin.height()) height=pin.height())
# Main array bl/br
for pin_name in self.all_bitcell_bitline_names: for pin_name in self.all_bitcell_bitline_names:
pin_list = self.bitcell_array_inst.get_pins(pin_name) pin_list = self.bitcell_array_inst.get_pins(pin_name)
for pin in pin_list: for pin in pin_list:
self.add_layout_pin(text=pin_name, self.add_layout_pin(text=pin_name,
layer=pin.layer, layer=pin.layer,
offset=pin.ll(), offset=pin.ll().scale(1, 0),
width=pin.width(), width=pin.width(),
height=self.height) height=self.height)
@ -373,7 +374,7 @@ class replica_bitcell_array(bitcell_base_array):
pin = inst.get_pin(pin_name) pin = inst.get_pin(pin_name)
self.add_layout_pin(text=bl_name, self.add_layout_pin(text=bl_name,
layer=pin.layer, layer=pin.layer,
offset=pin.ll(), offset=pin.ll().scale(1, 0),
width=pin.width(), width=pin.width(),
height=self.height) height=self.height)