mirror of https://github.com/VLSIDA/OpenRAM.git
Use sky130 bitcell in simulation for BLs
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parent
a874872936
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d119a0e7ff
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@ -482,7 +482,7 @@ class simulation():
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debug.warning("Error occurred while determining SEN name. Can cause faults in simulation.")
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debug.info(2, "s_en name = {}".format(self.sen_name))
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column_addr = self.get_column_addr()
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bl_name_port, br_name_port = self.get_bl_name(self.graph.all_paths, port)
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port_pos = -1 - len(str(column_addr)) - len(str(port))
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@ -576,7 +576,11 @@ class simulation():
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"""
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Gets the signal name associated with the bitlines in the bank.
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"""
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cell_mod = factory.create(module_type=OPTS.bitcell)
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# FIXME: change to a solution that does not depend on the technology
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if OPTS.tech_name == 'sky130':
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cell_mod = factory.create(module_type=OPTS.bitcell, version="opt1")
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else:
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cell_mod = factory.create(module_type=OPTS.bitcell)
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cell_bl = cell_mod.get_bl_name(port)
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cell_br = cell_mod.get_br_name(port)
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@ -588,14 +592,14 @@ class simulation():
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for i in range(len(bl_names)):
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bl_names[i] = bl_names[i].split(OPTS.hier_seperator)[-1]
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return bl_names[0], bl_names[1]
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def get_empty_measure_data_dict(self):
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"""Make a dict of lists for each type of delay and power measurement to append results to"""
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measure_names = self.delay_meas_names + self.power_meas_names
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# Create list of dicts. List lengths is # of ports. Each dict maps the measurement names to lists.
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measure_data = [{mname: [] for mname in measure_names} for i in self.all_ports]
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return measure_data
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return measure_data
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def sum_delays(self, delays):
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"""Adds the delays (delay_data objects) so the correct slew is maintained"""
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@ -604,5 +608,3 @@ class simulation():
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for i in range(1, len(delays)):
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delay+=delays[i]
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return delay
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