luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Use sky130 bitcell in simulation for BLs

This commit is contained in:
mrg 2021-06-16 18:45:53 -07:00
parent a874872936
commit d119a0e7ff
1 changed files with 8 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
compiler/characterizer/simulation.py
View File

@ -576,6 +576,10 @@ class simulation():
""" """
Gets the signal name associated with the bitlines in the bank. Gets the signal name associated with the bitlines in the bank.
""" """
# FIXME: change to a solution that does not depend on the technology
if OPTS.tech_name == 'sky130':
cell_mod = factory.create(module_type=OPTS.bitcell, version="opt1")
else:
cell_mod = factory.create(module_type=OPTS.bitcell) cell_mod = factory.create(module_type=OPTS.bitcell)
cell_bl = cell_mod.get_bl_name(port) cell_bl = cell_mod.get_bl_name(port)
cell_br = cell_mod.get_br_name(port) cell_br = cell_mod.get_br_name(port)
@ -604,5 +608,3 @@ class simulation():
for i in range(1, len(delays)): for i in range(1, len(delays)):
delay+=delays[i] delay+=delays[i]
return delay return delay