mirror of https://github.com/VLSIDA/OpenRAM.git
First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.
This commit is contained in:
Hunter Nichols
parent
62ad30e741
commit
d0e6dc9ce7
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@ -121,10 +121,9 @@ class design(hierarchy_spice.spice, hierarchy_layout.layout):
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text+=str(i)+",\n"
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return text
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def analytical_power(self, vdd, temp, load):
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def analytical_power(self, proc, vdd, temp, load):
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""" Get total power of a module """
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#print "Getting power for ",self.name," module"
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total_module_power = self.return_power()
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for inst in self.insts:
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total_module_power += inst.mod.analytical_power(vdd, temp, load)
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total_module_power += inst.mod.analytical_power(proc, vdd, temp, load)
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return total_module_power
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@ -550,19 +550,24 @@ class delay():
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LH_slew.append(bank_delay.slew/1e3)
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HL_slew.append(bank_delay.slew/1e3)
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voltage = 1
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temperature = 20
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power = sram.analytical_power(voltage, temperature, load)
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power = sram.analytical_power(self.process, self.vdd_voltage, self.temperature, load)
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#convert from nW to mW
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power.dynamic /= 1e6
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power.leakage /= 1e6
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debug.info(1,"Dynamic Power: {0} mW".format(power.dynamic))
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debug.info(1,"Leakage Power: {0} mW".format(power.leakage))
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#print "Dynamic: ",power.dynamic," nW"
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#print "Leakage: ",power.leakage," nW"
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data = {"min_period": 0,
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"delay1": LH_delay,
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"delay0": HL_delay,
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"slew1": LH_slew,
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"slew0": HL_slew,
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"read0_power": power,
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"read1_power": power,
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"write0_power": power,
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"write1_power": power
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"read0_power": power.dynamic,
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"read1_power": power.leakage,
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"write0_power": power.dynamic,
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"write1_power": power.leakage
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}
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return data
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@ -1229,22 +1229,3 @@ class bank(design.design):
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+ bitcell_array_delay + bl_t_data_out_delay + data_t_DATA_delay
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return result
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# def analytical_power(self, slew, load):
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# """ return analytical power of the bank. Basic skeleton code"""
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# msf_addr_power = self.msf_address.analytical_power(slew, self.decoder.input_load())
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# msf_data_in_power = self.msf_data_in.analytical_power(slew, self.decoder.input_load())
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# decoder_power = self.decoder.analytical_power(slew, load)
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# word_driver_power = self.wordline_driver.analytical_power(slew, self.bitcell_array.input_load())
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# bitcell_array_power = self.bitcell_array.analytical_power(slew)
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# bl_t_data_out_power = self.sense_amp_array.analytical_power(slew,
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# self.bitcell_array.output_load())
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# data_t_DATA_power = self.tri_gate_array.analytical_power(slew, load)
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# total_power = msf_addr_power + msf_data_in_power + decoder_power + word_driver_power \
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# + bitcell_array_power + bl_t_data_out_power + data_t_DATA_power
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# return total_power
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@ -35,7 +35,7 @@ class bitcell(design.design):
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result = self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew, swing = swing)
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return result
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def analytical_power(self, vdd, temp, load):
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def analytical_power(self, proc, vdd, temp, load):
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#Power of the bitcell. Mostly known for leakage, but dynamic can also be factored in.
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#Only consider leakage power for now. Value defined in tech file rather than calculated.
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from tech import spice
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@ -178,27 +178,27 @@ class bitcell_array(design.design):
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return self.return_delay(cell_delay.delay+wl_to_cell_delay.delay,
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wl_to_cell_delay.slew)
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def analytical_power(self, vdd, temp, load):
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def analytical_power(self, proc, vdd, temp, load):
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#This will be pretty bare bones as the power needs to be determined from the dynamic power
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#of the word line, leakage power from the cell, and dynamic power of the bitlines as a few
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#sources for power. These features are tbd.
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from tech import drc
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#calculate wl dynamic power, functions not implemented.
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#wl_wire = self.gen_wl_wire()
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#wl_to_cell_power = wl_wire.return_power_over_wire(slew)
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# hypothetical delay from cell to bl end without sense amp
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# Dynamic Power from Bitline
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bl_wire = self.gen_bl_wire()
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cell_load = 2 * bl_wire.return_input_cap() # we ingore the wire r
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# hence just use the whole c
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bl_swing = 0.1
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cell_load = 2 * bl_wire.return_input_cap()
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bl_swing = 0.1 #This should probably be defined in the tech file
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freq = spice["default_event_rate"]
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bitline_dynamic = bl_swing*cell_load*vdd*vdd*freq #not sure if calculation is correct
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#Calculate the bitcell power which can include leakage as well as bitline dynamic
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cell_power = self.cell.analytical_power(vdd, temp, load)
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cell_power = self.cell.analytical_power(proc, vdd, temp, load)
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#Leakage power grows with entire array. Dynamic currently not accounted for.
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total_power = self.return_power(cell_power.dynamic, cell_power.leakage * self.column_size * self.row_size)
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#calculate power for entire array based off a single cell
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total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
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cell_power.leakage * self.column_size * self.row_size)
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return total_power
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def gen_wl_wire(self):
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@ -688,13 +688,3 @@ class control_logic(design.design):
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width=pin.width())
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def analytical_power(self, vdd, temp, load):
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#This has yet to be fully determined.
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print "Instances:"
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total_power = self.return_power() #empty power object
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for inst in self.insts:
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print inst.name," Instance"
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total_power += inst.mod.analytical_power(vdd, temp, load)
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#currently, only return flop array power
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return total_power
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@ -494,21 +494,6 @@ class hierarchical_decoder(design.design):
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result = result + z_t_decodeout_delay
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return result
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# def analytical_power(self, slew, load = 0.0):
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# # A -> out
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# if self.determine_predecodes(self.num_inputs)[1]==0:
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# pre = self.pre2_4
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# nand = self.nand2
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# else:
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# pre = self.pre3_8
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# nand = self.nand3
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# a_t_out_power = pre.analytical_power(slew=slew,load = nand.input_load())
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# out_t_z_power = nand.analytical_power(slew,
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# load = self.inv.input_load())
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# z_t_decodeout_power = self.inv.analytical_power(slew, load = load)
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# return a_t_out_power + out_t_z_power + z_t_decodeout_power
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def input_load(self):
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if self.determine_predecodes(self.num_inputs)[1]==0:
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@ -55,17 +55,6 @@ class hierarchical_predecode2x4(hierarchical_predecode):
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return a_t_b_delay + b_t_z_delay + a_t_out_delay
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# def analytical_power(self, slew, load = 0.0 ):
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# # in -> inbar
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# a_t_b_power = self.inv.analytical_power(slew=slew, load=self.nand.input_load())
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# # inbar -> z
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# b_t_z_power = self.nand.analytical_power(slew, load=self.inv.input_load())
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# # Z -> out
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# a_t_out_power = self.inv.analytical_power(slew, load=load)
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# return a_t_b_power + b_t_z_power + a_t_out_power
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def input_load(self):
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return self.nand.input_load()
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@ -63,17 +63,6 @@ class hierarchical_predecode3x8(hierarchical_predecode):
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return a_t_b_delay + b_t_z_delay + a_t_out_delay
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# def analytical_power(self, slew, load = 0.0 ):
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# # in -> inbar
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# a_t_b_power = self.inv.analytical_power(slew=slew, load=self.nand.input_load())
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# # inbar -> z
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# b_t_z_power = self.nand.analytical_power(slew, load=self.inv.input_load())
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# # Z -> out
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# a_t_out_power = self.inv.analytical_power(slew, load=load)
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# return a_t_b_power + b_t_z_power + a_t_out_power
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def input_load(self):
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return self.nand.input_load()
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@ -27,11 +27,23 @@ class ms_flop(design.design):
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result = self.return_delay(spice["msflop_delay"], spice["msflop_slew"])
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return result
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def analytical_power(self, vdd, temp, load):
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#Value taken from tech file.
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def analytical_power(self, proc, vdd, temp, load):
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#Returns dynamic and leakage power. Results in nW
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from tech import spice
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return self.return_power()
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#return spice["msflop_power"]
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c_eff = self.calculate_effective_capacitance(load)
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f = spice["default_event_rate"]
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power_dyn = c_eff*vdd*vdd*f
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power_leak = spice["nor2_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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from tech import spice, parameter
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c_load = load
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c_para = spice["flop_para_cap"]#ff
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transistion_prob = spice["flop_transisition_prob"]
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return transistion_prob*(c_load + c_para)
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@ -135,5 +135,3 @@ class ms_flop_array(design.design):
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def analytical_delay(self, slew, load=0.0):
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return self.ms.analytical_delay(slew=slew, load=load)
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# def analytical_power(self, vdd, temp, load):
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# return self.columns * self.ms.analytical_power(slew=slew, load=load)
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@ -344,15 +344,3 @@ class replica_bitline(design.design):
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height=pin.height(),
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width=pin.width())
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# def analytical_power(self, vdd, temp, load):
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# #This has yet to be fully determined.
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# print self.name," Instances:"
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# total_power = self.return_power()
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# for inst in self.insts:
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# print inst.name," Instance"
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# total_power += inst.mod.analytical_power(vdd, temp, load)
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# print self.name," Instances End"
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# #currently, only return flop array power
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# return total_power
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@ -30,7 +30,7 @@ class sense_amp(design.design):
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result = self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew)
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return self.return_delay(result.delay, result.slew)
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def analytical_power(self, vdd, temp, load):
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def analytical_power(self, proc, vdd, temp, load):
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#Not sure how to determine this yet. Sense amps return zero power for now
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total_power = self.return_power()
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return total_power
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@ -118,5 +118,3 @@ class sense_amp_array(design.design):
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def analytical_delay(self, slew, load=0.0):
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return self.amp.analytical_delay(slew=slew, load=load)
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# def analytical_power(self, slew, load=0.0):
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# return self.amp.analytical_power(slew=slew, load=load)
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@ -33,7 +33,7 @@ class tri_gate(design.design):
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c_para = spice["min_tx_drain_c"]
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return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew)
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def analytical_power(self, vdd, temp, load):
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def analytical_power(self, proc, vdd, temp, load):
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#Not sure how to determine this yet. Tri-gates return zero power for now
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total_power = self.return_power()
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return total_power
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@ -112,5 +112,3 @@ class tri_gate_array(design.design):
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def analytical_delay(self, slew, load=0.0):
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return self.tri.analytical_delay(slew = slew, load = load)
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# def analytical_power(self, slew, load=0.0):
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# return self.tri.analytical_power(slew = slew, load = load)
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@ -206,14 +206,6 @@ class wordline_driver(design.design):
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return decode_t_net + net_t_wl
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# def analytical_power(self, slew, load=0):
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# # decode -> net
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# decode_p_net = self.nand2.analytical_power(slew, self.inv.input_load())
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# # net -> wl
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# net_p_wl = self.inv.analytical_power(slew, load)
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# return decode_p_net + net_p_wl
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def input_load(self):
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return self.nand2.input_load()
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@ -242,8 +242,8 @@ class pinv(pgate.pgate):
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew)
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def analytical_power(self, vdd, temp, load):
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#Adding a magic number until I can properly define this.
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def analytical_power(self, proc, vdd, temp, load):
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#Returns dynamic and leakage power. Results in nW
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c_eff = self.calculate_effective_capacitance(load)
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f = spice["default_event_rate"]
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power_dyn = c_eff*vdd*vdd*f
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@ -214,6 +214,18 @@ class pnand2(pgate.pgate):
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew)
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def analytical_power(self, vdd, temp, load):
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#Adding a magic number until I can properly define this.
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return self.return_power()
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def analytical_power(self, proc, vdd, temp, load):
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#Returns dynamic and leakage power. Results in nW
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c_eff = self.calculate_effective_capacitance(load)
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f = spice["default_event_rate"]
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power_dyn = c_eff*vdd*vdd*f
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power_leak = spice["nand2_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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c_load = load
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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transistion_prob = spice["nand2_transisition_prob"]
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return transistion_prob*(c_load + c_para)
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@ -234,6 +234,18 @@ class pnand3(pgate.pgate):
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew)
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def analytical_power(self, vdd, temp, load):
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#Adding a magic number until I can properly define this.
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return self.return_power()
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def analytical_power(self, proc, vdd, temp, load):
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#Returns dynamic and leakage power. Results in nW
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c_eff = self.calculate_effective_capacitance(load)
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f = spice["default_event_rate"]
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power_dyn = c_eff*vdd*vdd*f
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power_leak = spice["nand3_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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c_load = load
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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transistion_prob = spice["nand3_transisition_prob"]
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return transistion_prob*(c_load + c_para)
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@ -224,3 +224,19 @@ class pnor2(pgate.pgate):
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew)
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def analytical_power(self, proc, vdd, temp, load):
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#Returns dynamic and leakage power. Results in nW
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c_eff = self.calculate_effective_capacitance(load)
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f = spice["default_event_rate"]
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power_dyn = c_eff*vdd*vdd*f
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power_leak = spice["nor2_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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c_load = load
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c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
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transistion_prob = spice["nor2_transisition_prob"]
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return transistion_prob*(c_load + c_para)
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@ -1015,30 +1015,6 @@ class sram(design.design):
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""" LH and HL are the same in analytical model. """
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return self.bank.analytical_delay(slew,load)
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# def analytical_power(self, vdd, temp, load):
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# """ Just a test function for the power."""
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# power_sum = 0;
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# print "Module Powers"
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# # for mod in self.mods:
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# # print mod.name," Power: ", mod.analytical_power(slew, load)
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# # power_sum += mod.analytical_power(slew, load)
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# # print "Instances:"
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# # for inst in self.insts:
|
||||
# # print inst.name," Instance"
|
||||
|
||||
|
||||
# # print "Instances from Modules of Instances:"
|
||||
# # for inst in self.insts:
|
||||
# # print inst.mod.name," Module"
|
||||
# # for mod_inst in inst.mod.insts:
|
||||
# # print mod_inst.name," Instance"
|
||||
|
||||
|
||||
# power_sum = self.control_logic.analytical_power(vdd, temp, load)
|
||||
# return power_sum
|
||||
|
||||
def save_output(self):
|
||||
""" Save all the output files while reporting time to do it as well. """
|
||||
|
||||
|
|
|
|||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
|
|
@ -1,329 +0,0 @@
|
|||
library (sram_2_16_1_freepdk45_lib){
|
||||
delay_model : "table_lookup";
|
||||
time_unit : "1ns" ;
|
||||
voltage_unit : "1v" ;
|
||||
current_unit : "1mA" ;
|
||||
resistance_unit : "1kohm" ;
|
||||
capacitive_load_unit(1 ,fF) ;
|
||||
leakage_power_unit : "1mW" ;
|
||||
pulling_resistance_unit :"1kohm" ;
|
||||
operating_conditions(TT){
|
||||
voltage : 1.0 ;
|
||||
temperature : 25.000 ;
|
||||
}
|
||||
|
||||
input_threshold_pct_fall : 50.0 ;
|
||||
output_threshold_pct_fall : 50.0 ;
|
||||
input_threshold_pct_rise : 50.0 ;
|
||||
output_threshold_pct_rise : 50.0 ;
|
||||
slew_lower_threshold_pct_fall : 10.0 ;
|
||||
slew_upper_threshold_pct_fall : 90.0 ;
|
||||
slew_lower_threshold_pct_rise : 10.0 ;
|
||||
slew_upper_threshold_pct_rise : 90.0 ;
|
||||
|
||||
default_cell_leakage_power : 0.0 ;
|
||||
default_leakage_power_density : 0.0 ;
|
||||
default_input_pin_cap : 1.0 ;
|
||||
default_inout_pin_cap : 1.0 ;
|
||||
default_output_pin_cap : 0.0 ;
|
||||
default_max_transition : 0.5 ;
|
||||
default_fanout_load : 1.0 ;
|
||||
default_max_fanout : 4.0 ;
|
||||
default_connection_class : universal ;
|
||||
|
||||
lu_table_template(CELL_TABLE){
|
||||
variable_1 : input_net_transition;
|
||||
variable_2 : total_output_net_capacitance;
|
||||
index_1("0.00125, 0.005, 0.04");
|
||||
index_2("0.052275, 0.2091, 1.6728");
|
||||
}
|
||||
|
||||
lu_table_template(CONSTRAINT_TABLE){
|
||||
variable_1 : related_pin_transition;
|
||||
variable_2 : constrained_pin_transition;
|
||||
index_1("0.00125, 0.005, 0.04");
|
||||
index_2("0.00125, 0.005, 0.04");
|
||||
}
|
||||
|
||||
default_operating_conditions : TT;
|
||||
|
||||
|
||||
type (DATA){
|
||||
base_type : array;
|
||||
data_type : bit;
|
||||
bit_width : 2;
|
||||
bit_from : 0;
|
||||
bit_to : 1;
|
||||
}
|
||||
|
||||
type (ADDR){
|
||||
base_type : array;
|
||||
data_type : bit;
|
||||
bit_width : 7;
|
||||
bit_from : 0;
|
||||
bit_to : 6;
|
||||
}
|
||||
|
||||
cell (sram_2_16_1_freepdk45){
|
||||
memory(){
|
||||
type : ram;
|
||||
address_width : 7;
|
||||
word_width : 2;
|
||||
}
|
||||
interface_timing : true;
|
||||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 1756.7563625;
|
||||
|
||||
bus(DATA){
|
||||
bus_type : DATA;
|
||||
direction : inout;
|
||||
max_capacitance : 1.6728;
|
||||
three_state : "!OEb & !clk";
|
||||
memory_write(){
|
||||
address : ADDR;
|
||||
clocked_on : clk;
|
||||
}
|
||||
memory_read(){
|
||||
address : ADDR;
|
||||
}
|
||||
pin(DATA[1:0]){
|
||||
internal_power(){
|
||||
when : "OEb & !clk";
|
||||
rise_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!OEb & !clk";
|
||||
rise_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk";
|
||||
timing_type : falling_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.167, 0.168, 0.177",\
|
||||
"0.167, 0.168, 0.177",\
|
||||
"0.167, 0.168, 0.177");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("0.167, 0.168, 0.177",\
|
||||
"0.167, 0.168, 0.177",\
|
||||
"0.167, 0.168, 0.177");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.006, 0.007, 0.018",\
|
||||
"0.006, 0.007, 0.018",\
|
||||
"0.006, 0.007, 0.018");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.006, 0.007, 0.018",\
|
||||
"0.006, 0.007, 0.018",\
|
||||
"0.006, 0.007, 0.018");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bus(ADDR){
|
||||
bus_type : ADDR;
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
max_transition : 0.04;
|
||||
fanout_load : 1.000000;
|
||||
pin(ADDR[6:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(CSb){
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(OEb){
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(WEb){
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(clk){
|
||||
clock : true;
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk;
|
||||
rise_constraint(scalar) {
|
||||
values("0.0");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.0");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk;
|
||||
rise_constraint(scalar) {
|
||||
values("0.0");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.0");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,875 +0,0 @@
|
|||
**************************************************
|
||||
* OpenRAM generated memory.
|
||||
* Words: 128
|
||||
* Data bits: 2
|
||||
* Banks: 1
|
||||
* Column mux: 4:1
|
||||
**************************************************
|
||||
|
||||
* ptx M{0} {1} nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.0225p ad=0.0225p
|
||||
|
||||
* ptx M{0} {1} pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
|
||||
.SUBCKT pnand2_1 A B Z vdd gnd
|
||||
Mpnand2_pmos1 vdd A Z vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpnand2_pmos2 Z B vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpnand2_nmos1 Z B net1 gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.0225p ad=0.0225p
|
||||
Mpnand2_nmos2 net1 A gnd gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.0225p ad=0.0225p
|
||||
.ENDS pnand2_1
|
||||
|
||||
.SUBCKT pnand3_1 A B C Z vdd gnd
|
||||
Mpnand3_pmos1 vdd A Z vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpnand3_pmos2 Z B vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpnand3_pmos3 Z C vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpnand3_nmos1 Z C net1 gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.0225p ad=0.0225p
|
||||
Mpnand3_nmos2 net1 B net2 gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.0225p ad=0.0225p
|
||||
Mpnand3_nmos3 net2 A gnd gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.0225p ad=0.0225p
|
||||
.ENDS pnand3_1
|
||||
|
||||
* ptx M{0} {1} nmos_vtg m=1 w=0.09u l=0.05u pd=0.28u ps=0.28u as=0.01125p ad=0.01125p
|
||||
|
||||
* ptx M{0} {1} pmos_vtg m=1 w=0.405u l=0.05u pd=0.91u ps=0.91u as=0.050625p ad=0.050625p
|
||||
|
||||
.SUBCKT pnor2_1 A B Z vdd gnd
|
||||
Mpnor2_pmos1 vdd A net1 vdd pmos_vtg m=1 w=0.405u l=0.05u pd=0.91u ps=0.91u as=0.050625p ad=0.050625p
|
||||
Mpnor2_pmos2 net1 B Z vdd pmos_vtg m=1 w=0.405u l=0.05u pd=0.91u ps=0.91u as=0.050625p ad=0.050625p
|
||||
Mpnor2_nmos1 Z A gnd gnd nmos_vtg m=1 w=0.09u l=0.05u pd=0.28u ps=0.28u as=0.01125p ad=0.01125p
|
||||
Mpnor2_nmos2 Z B gnd gnd nmos_vtg m=1 w=0.09u l=0.05u pd=0.28u ps=0.28u as=0.01125p ad=0.01125p
|
||||
.ENDS pnor2_1
|
||||
|
||||
.SUBCKT pinv_1 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpinv_nmos Z A gnd gnd nmos_vtg m=1 w=0.09u l=0.05u pd=0.28u ps=0.28u as=0.01125p ad=0.01125p
|
||||
.ENDS pinv_1
|
||||
|
||||
* ptx M{0} {1} nmos_vtg m=2 w=0.09u l=0.05u pd=0.28u ps=0.28u as=0.01125p ad=0.01125p
|
||||
|
||||
* ptx M{0} {1} pmos_vtg m=2 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
|
||||
.SUBCKT pinv_2 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd pmos_vtg m=2 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpinv_nmos Z A gnd gnd nmos_vtg m=2 w=0.09u l=0.05u pd=0.28u ps=0.28u as=0.01125p ad=0.01125p
|
||||
.ENDS pinv_2
|
||||
|
||||
* ptx M{0} {1} nmos_vtg m=3 w=0.12u l=0.05u pd=0.34u ps=0.34u as=0.015p ad=0.015p
|
||||
|
||||
* ptx M{0} {1} pmos_vtg m=3 w=0.36u l=0.05u pd=0.82u ps=0.82u as=0.045p ad=0.045p
|
||||
|
||||
.SUBCKT pinv_3 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd pmos_vtg m=3 w=0.36u l=0.05u pd=0.82u ps=0.82u as=0.045p ad=0.045p
|
||||
Mpinv_nmos Z A gnd gnd nmos_vtg m=3 w=0.12u l=0.05u pd=0.34u ps=0.34u as=0.015p ad=0.015p
|
||||
.ENDS pinv_3
|
||||
|
||||
* ptx M{0} {1} nmos_vtg m=6 w=0.12u l=0.05u pd=0.34u ps=0.34u as=0.015p ad=0.015p
|
||||
|
||||
* ptx M{0} {1} pmos_vtg m=6 w=0.36u l=0.05u pd=0.82u ps=0.82u as=0.045p ad=0.045p
|
||||
|
||||
.SUBCKT pinv_4 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd pmos_vtg m=6 w=0.36u l=0.05u pd=0.82u ps=0.82u as=0.045p ad=0.045p
|
||||
Mpinv_nmos Z A gnd gnd nmos_vtg m=6 w=0.12u l=0.05u pd=0.34u ps=0.34u as=0.015p ad=0.015p
|
||||
.ENDS pinv_4
|
||||
|
||||
* ptx M{0} {1} nmos_vtg m=12 w=0.12u l=0.05u pd=0.34u ps=0.34u as=0.015p ad=0.015p
|
||||
|
||||
* ptx M{0} {1} pmos_vtg m=12 w=0.36u l=0.05u pd=0.82u ps=0.82u as=0.045p ad=0.045p
|
||||
|
||||
.SUBCKT pinv_5 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd pmos_vtg m=12 w=0.36u l=0.05u pd=0.82u ps=0.82u as=0.045p ad=0.045p
|
||||
Mpinv_nmos Z A gnd gnd nmos_vtg m=12 w=0.12u l=0.05u pd=0.34u ps=0.34u as=0.015p ad=0.015p
|
||||
.ENDS pinv_5
|
||||
*master-slave flip-flop with both output and inverted ouput
|
||||
|
||||
.SUBCKT ms_flop din dout dout_bar clk vdd gnd
|
||||
xmaster din mout mout_bar clk clk_bar vdd gnd dlatch
|
||||
xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch
|
||||
.ENDS flop
|
||||
|
||||
.SUBCKT dlatch din dout dout_bar clk clk_bar vdd gnd
|
||||
*clk inverter
|
||||
mPff1 clk_bar clk vdd vdd PMOS_VTG W=180.0n L=50n m=1
|
||||
mNff1 clk_bar clk gnd gnd NMOS_VTG W=90n L=50n m=1
|
||||
|
||||
*transmission gate 1
|
||||
mtmP1 din clk int1 vdd PMOS_VTG W=180.0n L=50n m=1
|
||||
mtmN1 din clk_bar int1 gnd NMOS_VTG W=90n L=50n m=1
|
||||
|
||||
*foward inverter
|
||||
mPff3 dout_bar int1 vdd vdd PMOS_VTG W=180.0n L=50n m=1
|
||||
mNff3 dout_bar int1 gnd gnd NMOS_VTG W=90n L=50n m=1
|
||||
|
||||
*backward inverter
|
||||
mPff4 dout dout_bar vdd vdd PMOS_VTG W=180.0n L=50n m=1
|
||||
mNf4 dout dout_bar gnd gnd NMOS_VTG W=90n L=50n m=1
|
||||
|
||||
*transmission gate 2
|
||||
mtmP2 int1 clk_bar dout vdd PMOS_VTG W=180.0n L=50n m=1
|
||||
mtmN2 int1 clk dout gnd NMOS_VTG W=90n L=50n m=1
|
||||
.ENDS dlatch
|
||||
|
||||
|
||||
.SUBCKT msf_control din[0] din[1] din[2] dout[0] dout_bar[0] dout[1] dout_bar[1] dout[2] dout_bar[2] clk vdd gnd
|
||||
XXdff0 din[0] dout[0] dout_bar[0] clk vdd gnd ms_flop
|
||||
XXdff1 din[1] dout[1] dout_bar[1] clk vdd gnd ms_flop
|
||||
XXdff2 din[2] dout[2] dout_bar[2] clk vdd gnd ms_flop
|
||||
.ENDS msf_control
|
||||
|
||||
.SUBCKT replica_cell_6t bl br wl vdd gnd
|
||||
MM3 bl wl gnd gnd NMOS_VTG W=135.00n L=50n
|
||||
MM2 br wl net4 gnd NMOS_VTG W=135.00n L=50n
|
||||
MM1 gnd net4 gnd gnd NMOS_VTG W=205.00n L=50n
|
||||
MM0 net4 gnd gnd gnd NMOS_VTG W=205.00n L=50n
|
||||
MM5 gnd net4 vdd vdd PMOS_VTG W=90n L=50n
|
||||
MM4 net4 gnd vdd vdd PMOS_VTG W=90n L=50n
|
||||
.ENDS replica_cell_6t
|
||||
|
||||
|
||||
.SUBCKT cell_6t bl br wl vdd gnd
|
||||
MM3 bl wl net10 gnd NMOS_VTG W=135.00n L=50n
|
||||
MM2 br wl net4 gnd NMOS_VTG W=135.00n L=50n
|
||||
MM1 net10 net4 gnd gnd NMOS_VTG W=205.00n L=50n
|
||||
MM0 net4 net10 gnd gnd NMOS_VTG W=205.00n L=50n
|
||||
MM5 net10 net4 vdd vdd PMOS_VTG W=90n L=50n
|
||||
MM4 net4 net10 vdd vdd PMOS_VTG W=90n L=50n
|
||||
.ENDS cell_6t
|
||||
|
||||
|
||||
.SUBCKT bitline_load bl[0] br[0] wl[0] wl[1] wl[2] wl[3] vdd gnd
|
||||
Xbit_r0_c0 bl[0] br[0] wl[0] vdd gnd cell_6t
|
||||
Xbit_r1_c0 bl[0] br[0] wl[1] vdd gnd cell_6t
|
||||
Xbit_r2_c0 bl[0] br[0] wl[2] vdd gnd cell_6t
|
||||
Xbit_r3_c0 bl[0] br[0] wl[3] vdd gnd cell_6t
|
||||
.ENDS bitline_load
|
||||
|
||||
.SUBCKT pinv_6 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpinv_nmos Z A gnd gnd nmos_vtg m=1 w=0.09u l=0.05u pd=0.28u ps=0.28u as=0.01125p ad=0.01125p
|
||||
.ENDS pinv_6
|
||||
|
||||
.SUBCKT delay_chain in out vdd gnd
|
||||
Xdinv0 in s1 vdd gnd pinv_6
|
||||
Xdinv1 s1 s2n1 vdd gnd pinv_6
|
||||
Xdinv2 s1 s2n2 vdd gnd pinv_6
|
||||
Xdinv3 s1 s2n3 vdd gnd pinv_6
|
||||
Xdinv4 s1 s2 vdd gnd pinv_6
|
||||
Xdinv5 s2 s3n1 vdd gnd pinv_6
|
||||
Xdinv6 s2 s3n2 vdd gnd pinv_6
|
||||
Xdinv7 s2 s3n3 vdd gnd pinv_6
|
||||
Xdinv8 s2 s3 vdd gnd pinv_6
|
||||
Xdinv9 s3 s4n1 vdd gnd pinv_6
|
||||
Xdinv10 s3 s4n2 vdd gnd pinv_6
|
||||
Xdinv11 s3 s4n3 vdd gnd pinv_6
|
||||
Xdinv12 s3 s4 vdd gnd pinv_6
|
||||
Xdinv13 s4 s5n1 vdd gnd pinv_6
|
||||
Xdinv14 s4 s5n2 vdd gnd pinv_6
|
||||
Xdinv15 s4 s5n3 vdd gnd pinv_6
|
||||
Xdinv16 s4 s5 vdd gnd pinv_6
|
||||
Xdinv17 s5 s6n1 vdd gnd pinv_6
|
||||
Xdinv18 s5 s6n2 vdd gnd pinv_6
|
||||
Xdinv19 s5 s6n3 vdd gnd pinv_6
|
||||
Xdinv20 s5 s6 vdd gnd pinv_6
|
||||
Xdinv21 s6 s7n1 vdd gnd pinv_6
|
||||
Xdinv22 s6 s7n2 vdd gnd pinv_6
|
||||
Xdinv23 s6 s7n3 vdd gnd pinv_6
|
||||
Xdinv24 s6 s7 vdd gnd pinv_6
|
||||
Xdinv25 s7 s8n1 vdd gnd pinv_6
|
||||
Xdinv26 s7 s8n2 vdd gnd pinv_6
|
||||
Xdinv27 s7 s8n3 vdd gnd pinv_6
|
||||
Xdinv28 s7 s8 vdd gnd pinv_6
|
||||
Xdinv29 s8 s9n1 vdd gnd pinv_6
|
||||
Xdinv30 s8 s9n2 vdd gnd pinv_6
|
||||
Xdinv31 s8 s9n3 vdd gnd pinv_6
|
||||
Xdinv32 s8 out vdd gnd pinv_6
|
||||
.ENDS delay_chain
|
||||
|
||||
.SUBCKT pinv_7 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpinv_nmos Z A gnd gnd nmos_vtg m=1 w=0.09u l=0.05u pd=0.28u ps=0.28u as=0.01125p ad=0.01125p
|
||||
.ENDS pinv_7
|
||||
|
||||
* ptx M{0} {1} pmos_vtg m=1 w=0.09u l=0.05u pd=0.28u ps=0.28u as=0.01125p ad=0.01125p
|
||||
|
||||
.SUBCKT replica_bitline en out vdd gnd
|
||||
Xrbl_inv bl[0] out vdd gnd pinv_7
|
||||
Mrbl_access_tx vdd delayed_en bl[0] vdd pmos_vtg m=1 w=0.09u l=0.05u pd=0.28u ps=0.28u as=0.01125p ad=0.01125p
|
||||
Xdelay_chain en delayed_en vdd gnd delay_chain
|
||||
Xbitcell bl[0] br[0] delayed_en vdd gnd replica_cell_6t
|
||||
Xload bl[0] br[0] gnd gnd gnd gnd vdd gnd bitline_load
|
||||
.ENDS replica_bitline
|
||||
|
||||
.SUBCKT control_logic csb web oeb clk s_en w_en tri_en tri_en_bar clk_bar clk_buf vdd gnd
|
||||
Xmsf_control oeb csb web oe_bar oe cs_bar cs we_bar we clk_buf vdd gnd msf_control
|
||||
Xinv_clk1_bar clk clk1_bar vdd gnd pinv_2
|
||||
Xinv_clk2 clk1_bar clk2 vdd gnd pinv_3
|
||||
Xinv_clk_bar clk2 clk_bar vdd gnd pinv_4
|
||||
Xinv_clk_buf clk_bar clk_buf vdd gnd pinv_5
|
||||
Xnand3_rblk_bar clk_bar oe cs rblk_bar vdd gnd pnand3_1
|
||||
Xinv_rblk rblk_bar rblk vdd gnd pinv_1
|
||||
Xnor2_tri_en clk_buf oe_bar tri_en vdd gnd pnor2_1
|
||||
Xnand2_tri_en clk_bar oe tri_en_bar vdd gnd pnand2_1
|
||||
Xinv_s_en pre_s_en_bar s_en vdd gnd pinv_1
|
||||
Xinv_pre_s_en_bar pre_s_en pre_s_en_bar vdd gnd pinv_1
|
||||
Xnand3_w_en_bar clk_bar cs we w_en_bar vdd gnd pnand3_1
|
||||
Xinv_pre_w_en w_en_bar pre_w_en vdd gnd pinv_1
|
||||
Xinv_pre_w_en_bar pre_w_en pre_w_en_bar vdd gnd pinv_1
|
||||
Xinv_w_en2 pre_w_en_bar w_en vdd gnd pinv_1
|
||||
Xreplica_bitline rblk pre_s_en vdd gnd replica_bitline
|
||||
.ENDS control_logic
|
||||
|
||||
.SUBCKT bitcell_array bl[0] br[0] bl[1] br[1] bl[2] br[2] bl[3] br[3] bl[4] br[4] bl[5] br[5] bl[6] br[6] bl[7] br[7] wl[0] wl[1] wl[2] wl[3] wl[4] wl[5] wl[6] wl[7] wl[8] wl[9] wl[10] wl[11] wl[12] wl[13] wl[14] wl[15] wl[16] wl[17] wl[18] wl[19] wl[20] wl[21] wl[22] wl[23] wl[24] wl[25] wl[26] wl[27] wl[28] wl[29] wl[30] wl[31] vdd gnd
|
||||
Xbit_r0_c0 bl[0] br[0] wl[0] vdd gnd cell_6t
|
||||
Xbit_r1_c0 bl[0] br[0] wl[1] vdd gnd cell_6t
|
||||
Xbit_r2_c0 bl[0] br[0] wl[2] vdd gnd cell_6t
|
||||
Xbit_r3_c0 bl[0] br[0] wl[3] vdd gnd cell_6t
|
||||
Xbit_r4_c0 bl[0] br[0] wl[4] vdd gnd cell_6t
|
||||
Xbit_r5_c0 bl[0] br[0] wl[5] vdd gnd cell_6t
|
||||
Xbit_r6_c0 bl[0] br[0] wl[6] vdd gnd cell_6t
|
||||
Xbit_r7_c0 bl[0] br[0] wl[7] vdd gnd cell_6t
|
||||
Xbit_r8_c0 bl[0] br[0] wl[8] vdd gnd cell_6t
|
||||
Xbit_r9_c0 bl[0] br[0] wl[9] vdd gnd cell_6t
|
||||
Xbit_r10_c0 bl[0] br[0] wl[10] vdd gnd cell_6t
|
||||
Xbit_r11_c0 bl[0] br[0] wl[11] vdd gnd cell_6t
|
||||
Xbit_r12_c0 bl[0] br[0] wl[12] vdd gnd cell_6t
|
||||
Xbit_r13_c0 bl[0] br[0] wl[13] vdd gnd cell_6t
|
||||
Xbit_r14_c0 bl[0] br[0] wl[14] vdd gnd cell_6t
|
||||
Xbit_r15_c0 bl[0] br[0] wl[15] vdd gnd cell_6t
|
||||
Xbit_r16_c0 bl[0] br[0] wl[16] vdd gnd cell_6t
|
||||
Xbit_r17_c0 bl[0] br[0] wl[17] vdd gnd cell_6t
|
||||
Xbit_r18_c0 bl[0] br[0] wl[18] vdd gnd cell_6t
|
||||
Xbit_r19_c0 bl[0] br[0] wl[19] vdd gnd cell_6t
|
||||
Xbit_r20_c0 bl[0] br[0] wl[20] vdd gnd cell_6t
|
||||
Xbit_r21_c0 bl[0] br[0] wl[21] vdd gnd cell_6t
|
||||
Xbit_r22_c0 bl[0] br[0] wl[22] vdd gnd cell_6t
|
||||
Xbit_r23_c0 bl[0] br[0] wl[23] vdd gnd cell_6t
|
||||
Xbit_r24_c0 bl[0] br[0] wl[24] vdd gnd cell_6t
|
||||
Xbit_r25_c0 bl[0] br[0] wl[25] vdd gnd cell_6t
|
||||
Xbit_r26_c0 bl[0] br[0] wl[26] vdd gnd cell_6t
|
||||
Xbit_r27_c0 bl[0] br[0] wl[27] vdd gnd cell_6t
|
||||
Xbit_r28_c0 bl[0] br[0] wl[28] vdd gnd cell_6t
|
||||
Xbit_r29_c0 bl[0] br[0] wl[29] vdd gnd cell_6t
|
||||
Xbit_r30_c0 bl[0] br[0] wl[30] vdd gnd cell_6t
|
||||
Xbit_r31_c0 bl[0] br[0] wl[31] vdd gnd cell_6t
|
||||
Xbit_r0_c1 bl[1] br[1] wl[0] vdd gnd cell_6t
|
||||
Xbit_r1_c1 bl[1] br[1] wl[1] vdd gnd cell_6t
|
||||
Xbit_r2_c1 bl[1] br[1] wl[2] vdd gnd cell_6t
|
||||
Xbit_r3_c1 bl[1] br[1] wl[3] vdd gnd cell_6t
|
||||
Xbit_r4_c1 bl[1] br[1] wl[4] vdd gnd cell_6t
|
||||
Xbit_r5_c1 bl[1] br[1] wl[5] vdd gnd cell_6t
|
||||
Xbit_r6_c1 bl[1] br[1] wl[6] vdd gnd cell_6t
|
||||
Xbit_r7_c1 bl[1] br[1] wl[7] vdd gnd cell_6t
|
||||
Xbit_r8_c1 bl[1] br[1] wl[8] vdd gnd cell_6t
|
||||
Xbit_r9_c1 bl[1] br[1] wl[9] vdd gnd cell_6t
|
||||
Xbit_r10_c1 bl[1] br[1] wl[10] vdd gnd cell_6t
|
||||
Xbit_r11_c1 bl[1] br[1] wl[11] vdd gnd cell_6t
|
||||
Xbit_r12_c1 bl[1] br[1] wl[12] vdd gnd cell_6t
|
||||
Xbit_r13_c1 bl[1] br[1] wl[13] vdd gnd cell_6t
|
||||
Xbit_r14_c1 bl[1] br[1] wl[14] vdd gnd cell_6t
|
||||
Xbit_r15_c1 bl[1] br[1] wl[15] vdd gnd cell_6t
|
||||
Xbit_r16_c1 bl[1] br[1] wl[16] vdd gnd cell_6t
|
||||
Xbit_r17_c1 bl[1] br[1] wl[17] vdd gnd cell_6t
|
||||
Xbit_r18_c1 bl[1] br[1] wl[18] vdd gnd cell_6t
|
||||
Xbit_r19_c1 bl[1] br[1] wl[19] vdd gnd cell_6t
|
||||
Xbit_r20_c1 bl[1] br[1] wl[20] vdd gnd cell_6t
|
||||
Xbit_r21_c1 bl[1] br[1] wl[21] vdd gnd cell_6t
|
||||
Xbit_r22_c1 bl[1] br[1] wl[22] vdd gnd cell_6t
|
||||
Xbit_r23_c1 bl[1] br[1] wl[23] vdd gnd cell_6t
|
||||
Xbit_r24_c1 bl[1] br[1] wl[24] vdd gnd cell_6t
|
||||
Xbit_r25_c1 bl[1] br[1] wl[25] vdd gnd cell_6t
|
||||
Xbit_r26_c1 bl[1] br[1] wl[26] vdd gnd cell_6t
|
||||
Xbit_r27_c1 bl[1] br[1] wl[27] vdd gnd cell_6t
|
||||
Xbit_r28_c1 bl[1] br[1] wl[28] vdd gnd cell_6t
|
||||
Xbit_r29_c1 bl[1] br[1] wl[29] vdd gnd cell_6t
|
||||
Xbit_r30_c1 bl[1] br[1] wl[30] vdd gnd cell_6t
|
||||
Xbit_r31_c1 bl[1] br[1] wl[31] vdd gnd cell_6t
|
||||
Xbit_r0_c2 bl[2] br[2] wl[0] vdd gnd cell_6t
|
||||
Xbit_r1_c2 bl[2] br[2] wl[1] vdd gnd cell_6t
|
||||
Xbit_r2_c2 bl[2] br[2] wl[2] vdd gnd cell_6t
|
||||
Xbit_r3_c2 bl[2] br[2] wl[3] vdd gnd cell_6t
|
||||
Xbit_r4_c2 bl[2] br[2] wl[4] vdd gnd cell_6t
|
||||
Xbit_r5_c2 bl[2] br[2] wl[5] vdd gnd cell_6t
|
||||
Xbit_r6_c2 bl[2] br[2] wl[6] vdd gnd cell_6t
|
||||
Xbit_r7_c2 bl[2] br[2] wl[7] vdd gnd cell_6t
|
||||
Xbit_r8_c2 bl[2] br[2] wl[8] vdd gnd cell_6t
|
||||
Xbit_r9_c2 bl[2] br[2] wl[9] vdd gnd cell_6t
|
||||
Xbit_r10_c2 bl[2] br[2] wl[10] vdd gnd cell_6t
|
||||
Xbit_r11_c2 bl[2] br[2] wl[11] vdd gnd cell_6t
|
||||
Xbit_r12_c2 bl[2] br[2] wl[12] vdd gnd cell_6t
|
||||
Xbit_r13_c2 bl[2] br[2] wl[13] vdd gnd cell_6t
|
||||
Xbit_r14_c2 bl[2] br[2] wl[14] vdd gnd cell_6t
|
||||
Xbit_r15_c2 bl[2] br[2] wl[15] vdd gnd cell_6t
|
||||
Xbit_r16_c2 bl[2] br[2] wl[16] vdd gnd cell_6t
|
||||
Xbit_r17_c2 bl[2] br[2] wl[17] vdd gnd cell_6t
|
||||
Xbit_r18_c2 bl[2] br[2] wl[18] vdd gnd cell_6t
|
||||
Xbit_r19_c2 bl[2] br[2] wl[19] vdd gnd cell_6t
|
||||
Xbit_r20_c2 bl[2] br[2] wl[20] vdd gnd cell_6t
|
||||
Xbit_r21_c2 bl[2] br[2] wl[21] vdd gnd cell_6t
|
||||
Xbit_r22_c2 bl[2] br[2] wl[22] vdd gnd cell_6t
|
||||
Xbit_r23_c2 bl[2] br[2] wl[23] vdd gnd cell_6t
|
||||
Xbit_r24_c2 bl[2] br[2] wl[24] vdd gnd cell_6t
|
||||
Xbit_r25_c2 bl[2] br[2] wl[25] vdd gnd cell_6t
|
||||
Xbit_r26_c2 bl[2] br[2] wl[26] vdd gnd cell_6t
|
||||
Xbit_r27_c2 bl[2] br[2] wl[27] vdd gnd cell_6t
|
||||
Xbit_r28_c2 bl[2] br[2] wl[28] vdd gnd cell_6t
|
||||
Xbit_r29_c2 bl[2] br[2] wl[29] vdd gnd cell_6t
|
||||
Xbit_r30_c2 bl[2] br[2] wl[30] vdd gnd cell_6t
|
||||
Xbit_r31_c2 bl[2] br[2] wl[31] vdd gnd cell_6t
|
||||
Xbit_r0_c3 bl[3] br[3] wl[0] vdd gnd cell_6t
|
||||
Xbit_r1_c3 bl[3] br[3] wl[1] vdd gnd cell_6t
|
||||
Xbit_r2_c3 bl[3] br[3] wl[2] vdd gnd cell_6t
|
||||
Xbit_r3_c3 bl[3] br[3] wl[3] vdd gnd cell_6t
|
||||
Xbit_r4_c3 bl[3] br[3] wl[4] vdd gnd cell_6t
|
||||
Xbit_r5_c3 bl[3] br[3] wl[5] vdd gnd cell_6t
|
||||
Xbit_r6_c3 bl[3] br[3] wl[6] vdd gnd cell_6t
|
||||
Xbit_r7_c3 bl[3] br[3] wl[7] vdd gnd cell_6t
|
||||
Xbit_r8_c3 bl[3] br[3] wl[8] vdd gnd cell_6t
|
||||
Xbit_r9_c3 bl[3] br[3] wl[9] vdd gnd cell_6t
|
||||
Xbit_r10_c3 bl[3] br[3] wl[10] vdd gnd cell_6t
|
||||
Xbit_r11_c3 bl[3] br[3] wl[11] vdd gnd cell_6t
|
||||
Xbit_r12_c3 bl[3] br[3] wl[12] vdd gnd cell_6t
|
||||
Xbit_r13_c3 bl[3] br[3] wl[13] vdd gnd cell_6t
|
||||
Xbit_r14_c3 bl[3] br[3] wl[14] vdd gnd cell_6t
|
||||
Xbit_r15_c3 bl[3] br[3] wl[15] vdd gnd cell_6t
|
||||
Xbit_r16_c3 bl[3] br[3] wl[16] vdd gnd cell_6t
|
||||
Xbit_r17_c3 bl[3] br[3] wl[17] vdd gnd cell_6t
|
||||
Xbit_r18_c3 bl[3] br[3] wl[18] vdd gnd cell_6t
|
||||
Xbit_r19_c3 bl[3] br[3] wl[19] vdd gnd cell_6t
|
||||
Xbit_r20_c3 bl[3] br[3] wl[20] vdd gnd cell_6t
|
||||
Xbit_r21_c3 bl[3] br[3] wl[21] vdd gnd cell_6t
|
||||
Xbit_r22_c3 bl[3] br[3] wl[22] vdd gnd cell_6t
|
||||
Xbit_r23_c3 bl[3] br[3] wl[23] vdd gnd cell_6t
|
||||
Xbit_r24_c3 bl[3] br[3] wl[24] vdd gnd cell_6t
|
||||
Xbit_r25_c3 bl[3] br[3] wl[25] vdd gnd cell_6t
|
||||
Xbit_r26_c3 bl[3] br[3] wl[26] vdd gnd cell_6t
|
||||
Xbit_r27_c3 bl[3] br[3] wl[27] vdd gnd cell_6t
|
||||
Xbit_r28_c3 bl[3] br[3] wl[28] vdd gnd cell_6t
|
||||
Xbit_r29_c3 bl[3] br[3] wl[29] vdd gnd cell_6t
|
||||
Xbit_r30_c3 bl[3] br[3] wl[30] vdd gnd cell_6t
|
||||
Xbit_r31_c3 bl[3] br[3] wl[31] vdd gnd cell_6t
|
||||
Xbit_r0_c4 bl[4] br[4] wl[0] vdd gnd cell_6t
|
||||
Xbit_r1_c4 bl[4] br[4] wl[1] vdd gnd cell_6t
|
||||
Xbit_r2_c4 bl[4] br[4] wl[2] vdd gnd cell_6t
|
||||
Xbit_r3_c4 bl[4] br[4] wl[3] vdd gnd cell_6t
|
||||
Xbit_r4_c4 bl[4] br[4] wl[4] vdd gnd cell_6t
|
||||
Xbit_r5_c4 bl[4] br[4] wl[5] vdd gnd cell_6t
|
||||
Xbit_r6_c4 bl[4] br[4] wl[6] vdd gnd cell_6t
|
||||
Xbit_r7_c4 bl[4] br[4] wl[7] vdd gnd cell_6t
|
||||
Xbit_r8_c4 bl[4] br[4] wl[8] vdd gnd cell_6t
|
||||
Xbit_r9_c4 bl[4] br[4] wl[9] vdd gnd cell_6t
|
||||
Xbit_r10_c4 bl[4] br[4] wl[10] vdd gnd cell_6t
|
||||
Xbit_r11_c4 bl[4] br[4] wl[11] vdd gnd cell_6t
|
||||
Xbit_r12_c4 bl[4] br[4] wl[12] vdd gnd cell_6t
|
||||
Xbit_r13_c4 bl[4] br[4] wl[13] vdd gnd cell_6t
|
||||
Xbit_r14_c4 bl[4] br[4] wl[14] vdd gnd cell_6t
|
||||
Xbit_r15_c4 bl[4] br[4] wl[15] vdd gnd cell_6t
|
||||
Xbit_r16_c4 bl[4] br[4] wl[16] vdd gnd cell_6t
|
||||
Xbit_r17_c4 bl[4] br[4] wl[17] vdd gnd cell_6t
|
||||
Xbit_r18_c4 bl[4] br[4] wl[18] vdd gnd cell_6t
|
||||
Xbit_r19_c4 bl[4] br[4] wl[19] vdd gnd cell_6t
|
||||
Xbit_r20_c4 bl[4] br[4] wl[20] vdd gnd cell_6t
|
||||
Xbit_r21_c4 bl[4] br[4] wl[21] vdd gnd cell_6t
|
||||
Xbit_r22_c4 bl[4] br[4] wl[22] vdd gnd cell_6t
|
||||
Xbit_r23_c4 bl[4] br[4] wl[23] vdd gnd cell_6t
|
||||
Xbit_r24_c4 bl[4] br[4] wl[24] vdd gnd cell_6t
|
||||
Xbit_r25_c4 bl[4] br[4] wl[25] vdd gnd cell_6t
|
||||
Xbit_r26_c4 bl[4] br[4] wl[26] vdd gnd cell_6t
|
||||
Xbit_r27_c4 bl[4] br[4] wl[27] vdd gnd cell_6t
|
||||
Xbit_r28_c4 bl[4] br[4] wl[28] vdd gnd cell_6t
|
||||
Xbit_r29_c4 bl[4] br[4] wl[29] vdd gnd cell_6t
|
||||
Xbit_r30_c4 bl[4] br[4] wl[30] vdd gnd cell_6t
|
||||
Xbit_r31_c4 bl[4] br[4] wl[31] vdd gnd cell_6t
|
||||
Xbit_r0_c5 bl[5] br[5] wl[0] vdd gnd cell_6t
|
||||
Xbit_r1_c5 bl[5] br[5] wl[1] vdd gnd cell_6t
|
||||
Xbit_r2_c5 bl[5] br[5] wl[2] vdd gnd cell_6t
|
||||
Xbit_r3_c5 bl[5] br[5] wl[3] vdd gnd cell_6t
|
||||
Xbit_r4_c5 bl[5] br[5] wl[4] vdd gnd cell_6t
|
||||
Xbit_r5_c5 bl[5] br[5] wl[5] vdd gnd cell_6t
|
||||
Xbit_r6_c5 bl[5] br[5] wl[6] vdd gnd cell_6t
|
||||
Xbit_r7_c5 bl[5] br[5] wl[7] vdd gnd cell_6t
|
||||
Xbit_r8_c5 bl[5] br[5] wl[8] vdd gnd cell_6t
|
||||
Xbit_r9_c5 bl[5] br[5] wl[9] vdd gnd cell_6t
|
||||
Xbit_r10_c5 bl[5] br[5] wl[10] vdd gnd cell_6t
|
||||
Xbit_r11_c5 bl[5] br[5] wl[11] vdd gnd cell_6t
|
||||
Xbit_r12_c5 bl[5] br[5] wl[12] vdd gnd cell_6t
|
||||
Xbit_r13_c5 bl[5] br[5] wl[13] vdd gnd cell_6t
|
||||
Xbit_r14_c5 bl[5] br[5] wl[14] vdd gnd cell_6t
|
||||
Xbit_r15_c5 bl[5] br[5] wl[15] vdd gnd cell_6t
|
||||
Xbit_r16_c5 bl[5] br[5] wl[16] vdd gnd cell_6t
|
||||
Xbit_r17_c5 bl[5] br[5] wl[17] vdd gnd cell_6t
|
||||
Xbit_r18_c5 bl[5] br[5] wl[18] vdd gnd cell_6t
|
||||
Xbit_r19_c5 bl[5] br[5] wl[19] vdd gnd cell_6t
|
||||
Xbit_r20_c5 bl[5] br[5] wl[20] vdd gnd cell_6t
|
||||
Xbit_r21_c5 bl[5] br[5] wl[21] vdd gnd cell_6t
|
||||
Xbit_r22_c5 bl[5] br[5] wl[22] vdd gnd cell_6t
|
||||
Xbit_r23_c5 bl[5] br[5] wl[23] vdd gnd cell_6t
|
||||
Xbit_r24_c5 bl[5] br[5] wl[24] vdd gnd cell_6t
|
||||
Xbit_r25_c5 bl[5] br[5] wl[25] vdd gnd cell_6t
|
||||
Xbit_r26_c5 bl[5] br[5] wl[26] vdd gnd cell_6t
|
||||
Xbit_r27_c5 bl[5] br[5] wl[27] vdd gnd cell_6t
|
||||
Xbit_r28_c5 bl[5] br[5] wl[28] vdd gnd cell_6t
|
||||
Xbit_r29_c5 bl[5] br[5] wl[29] vdd gnd cell_6t
|
||||
Xbit_r30_c5 bl[5] br[5] wl[30] vdd gnd cell_6t
|
||||
Xbit_r31_c5 bl[5] br[5] wl[31] vdd gnd cell_6t
|
||||
Xbit_r0_c6 bl[6] br[6] wl[0] vdd gnd cell_6t
|
||||
Xbit_r1_c6 bl[6] br[6] wl[1] vdd gnd cell_6t
|
||||
Xbit_r2_c6 bl[6] br[6] wl[2] vdd gnd cell_6t
|
||||
Xbit_r3_c6 bl[6] br[6] wl[3] vdd gnd cell_6t
|
||||
Xbit_r4_c6 bl[6] br[6] wl[4] vdd gnd cell_6t
|
||||
Xbit_r5_c6 bl[6] br[6] wl[5] vdd gnd cell_6t
|
||||
Xbit_r6_c6 bl[6] br[6] wl[6] vdd gnd cell_6t
|
||||
Xbit_r7_c6 bl[6] br[6] wl[7] vdd gnd cell_6t
|
||||
Xbit_r8_c6 bl[6] br[6] wl[8] vdd gnd cell_6t
|
||||
Xbit_r9_c6 bl[6] br[6] wl[9] vdd gnd cell_6t
|
||||
Xbit_r10_c6 bl[6] br[6] wl[10] vdd gnd cell_6t
|
||||
Xbit_r11_c6 bl[6] br[6] wl[11] vdd gnd cell_6t
|
||||
Xbit_r12_c6 bl[6] br[6] wl[12] vdd gnd cell_6t
|
||||
Xbit_r13_c6 bl[6] br[6] wl[13] vdd gnd cell_6t
|
||||
Xbit_r14_c6 bl[6] br[6] wl[14] vdd gnd cell_6t
|
||||
Xbit_r15_c6 bl[6] br[6] wl[15] vdd gnd cell_6t
|
||||
Xbit_r16_c6 bl[6] br[6] wl[16] vdd gnd cell_6t
|
||||
Xbit_r17_c6 bl[6] br[6] wl[17] vdd gnd cell_6t
|
||||
Xbit_r18_c6 bl[6] br[6] wl[18] vdd gnd cell_6t
|
||||
Xbit_r19_c6 bl[6] br[6] wl[19] vdd gnd cell_6t
|
||||
Xbit_r20_c6 bl[6] br[6] wl[20] vdd gnd cell_6t
|
||||
Xbit_r21_c6 bl[6] br[6] wl[21] vdd gnd cell_6t
|
||||
Xbit_r22_c6 bl[6] br[6] wl[22] vdd gnd cell_6t
|
||||
Xbit_r23_c6 bl[6] br[6] wl[23] vdd gnd cell_6t
|
||||
Xbit_r24_c6 bl[6] br[6] wl[24] vdd gnd cell_6t
|
||||
Xbit_r25_c6 bl[6] br[6] wl[25] vdd gnd cell_6t
|
||||
Xbit_r26_c6 bl[6] br[6] wl[26] vdd gnd cell_6t
|
||||
Xbit_r27_c6 bl[6] br[6] wl[27] vdd gnd cell_6t
|
||||
Xbit_r28_c6 bl[6] br[6] wl[28] vdd gnd cell_6t
|
||||
Xbit_r29_c6 bl[6] br[6] wl[29] vdd gnd cell_6t
|
||||
Xbit_r30_c6 bl[6] br[6] wl[30] vdd gnd cell_6t
|
||||
Xbit_r31_c6 bl[6] br[6] wl[31] vdd gnd cell_6t
|
||||
Xbit_r0_c7 bl[7] br[7] wl[0] vdd gnd cell_6t
|
||||
Xbit_r1_c7 bl[7] br[7] wl[1] vdd gnd cell_6t
|
||||
Xbit_r2_c7 bl[7] br[7] wl[2] vdd gnd cell_6t
|
||||
Xbit_r3_c7 bl[7] br[7] wl[3] vdd gnd cell_6t
|
||||
Xbit_r4_c7 bl[7] br[7] wl[4] vdd gnd cell_6t
|
||||
Xbit_r5_c7 bl[7] br[7] wl[5] vdd gnd cell_6t
|
||||
Xbit_r6_c7 bl[7] br[7] wl[6] vdd gnd cell_6t
|
||||
Xbit_r7_c7 bl[7] br[7] wl[7] vdd gnd cell_6t
|
||||
Xbit_r8_c7 bl[7] br[7] wl[8] vdd gnd cell_6t
|
||||
Xbit_r9_c7 bl[7] br[7] wl[9] vdd gnd cell_6t
|
||||
Xbit_r10_c7 bl[7] br[7] wl[10] vdd gnd cell_6t
|
||||
Xbit_r11_c7 bl[7] br[7] wl[11] vdd gnd cell_6t
|
||||
Xbit_r12_c7 bl[7] br[7] wl[12] vdd gnd cell_6t
|
||||
Xbit_r13_c7 bl[7] br[7] wl[13] vdd gnd cell_6t
|
||||
Xbit_r14_c7 bl[7] br[7] wl[14] vdd gnd cell_6t
|
||||
Xbit_r15_c7 bl[7] br[7] wl[15] vdd gnd cell_6t
|
||||
Xbit_r16_c7 bl[7] br[7] wl[16] vdd gnd cell_6t
|
||||
Xbit_r17_c7 bl[7] br[7] wl[17] vdd gnd cell_6t
|
||||
Xbit_r18_c7 bl[7] br[7] wl[18] vdd gnd cell_6t
|
||||
Xbit_r19_c7 bl[7] br[7] wl[19] vdd gnd cell_6t
|
||||
Xbit_r20_c7 bl[7] br[7] wl[20] vdd gnd cell_6t
|
||||
Xbit_r21_c7 bl[7] br[7] wl[21] vdd gnd cell_6t
|
||||
Xbit_r22_c7 bl[7] br[7] wl[22] vdd gnd cell_6t
|
||||
Xbit_r23_c7 bl[7] br[7] wl[23] vdd gnd cell_6t
|
||||
Xbit_r24_c7 bl[7] br[7] wl[24] vdd gnd cell_6t
|
||||
Xbit_r25_c7 bl[7] br[7] wl[25] vdd gnd cell_6t
|
||||
Xbit_r26_c7 bl[7] br[7] wl[26] vdd gnd cell_6t
|
||||
Xbit_r27_c7 bl[7] br[7] wl[27] vdd gnd cell_6t
|
||||
Xbit_r28_c7 bl[7] br[7] wl[28] vdd gnd cell_6t
|
||||
Xbit_r29_c7 bl[7] br[7] wl[29] vdd gnd cell_6t
|
||||
Xbit_r30_c7 bl[7] br[7] wl[30] vdd gnd cell_6t
|
||||
Xbit_r31_c7 bl[7] br[7] wl[31] vdd gnd cell_6t
|
||||
.ENDS bitcell_array
|
||||
|
||||
* ptx M{0} {1} pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
|
||||
.SUBCKT precharge bl br en vdd
|
||||
Mlower_pmos bl en BR vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mupper_pmos1 bl en vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mupper_pmos2 br en vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
.ENDS precharge
|
||||
|
||||
.SUBCKT precharge_array bl[0] br[0] bl[1] br[1] bl[2] br[2] bl[3] br[3] bl[4] br[4] bl[5] br[5] bl[6] br[6] bl[7] br[7] en vdd
|
||||
Xpre_column_0 bl[0] br[0] en vdd precharge
|
||||
Xpre_column_1 bl[1] br[1] en vdd precharge
|
||||
Xpre_column_2 bl[2] br[2] en vdd precharge
|
||||
Xpre_column_3 bl[3] br[3] en vdd precharge
|
||||
Xpre_column_4 bl[4] br[4] en vdd precharge
|
||||
Xpre_column_5 bl[5] br[5] en vdd precharge
|
||||
Xpre_column_6 bl[6] br[6] en vdd precharge
|
||||
Xpre_column_7 bl[7] br[7] en vdd precharge
|
||||
.ENDS precharge_array
|
||||
|
||||
* ptx M{0} {1} nmos_vtg m=1 w=0.72u l=0.05u pd=1.54u ps=1.54u as=0.09p ad=0.09p
|
||||
|
||||
.SUBCKT single_level_column_mux_8 bl br bl_out br_out sel gnd
|
||||
Mmux_tx1 bl sel bl_out gnd nmos_vtg m=1 w=0.72u l=0.05u pd=1.54u ps=1.54u as=0.09p ad=0.09p
|
||||
Mmux_tx2 br sel br_out gnd nmos_vtg m=1 w=0.72u l=0.05u pd=1.54u ps=1.54u as=0.09p ad=0.09p
|
||||
.ENDS single_level_column_mux_8
|
||||
|
||||
.SUBCKT columnmux_array bl[0] br[0] bl[1] br[1] bl[2] br[2] bl[3] br[3] bl[4] br[4] bl[5] br[5] bl[6] br[6] bl[7] br[7] sel[0] sel[1] sel[2] sel[3] bl_out[0] br_out[0] bl_out[1] br_out[1] gnd
|
||||
XXMUX0 bl[0] br[0] bl_out[0] br_out[0] sel[0] gnd single_level_column_mux_8
|
||||
XXMUX1 bl[1] br[1] bl_out[0] br_out[0] sel[1] gnd single_level_column_mux_8
|
||||
XXMUX2 bl[2] br[2] bl_out[0] br_out[0] sel[2] gnd single_level_column_mux_8
|
||||
XXMUX3 bl[3] br[3] bl_out[0] br_out[0] sel[3] gnd single_level_column_mux_8
|
||||
XXMUX4 bl[4] br[4] bl_out[1] br_out[1] sel[0] gnd single_level_column_mux_8
|
||||
XXMUX5 bl[5] br[5] bl_out[1] br_out[1] sel[1] gnd single_level_column_mux_8
|
||||
XXMUX6 bl[6] br[6] bl_out[1] br_out[1] sel[2] gnd single_level_column_mux_8
|
||||
XXMUX7 bl[7] br[7] bl_out[1] br_out[1] sel[3] gnd single_level_column_mux_8
|
||||
.ENDS columnmux_array
|
||||
|
||||
.SUBCKT sense_amp bl br dout en vdd gnd
|
||||
M_1 dout net_1 vdd vdd pmos_vtg w=540.0n l=50.0n
|
||||
M_3 net_1 dout vdd vdd pmos_vtg w=540.0n l=50.0n
|
||||
M_2 dout net_1 net_2 gnd nmos_vtg w=270.0n l=50.0n
|
||||
M_8 net_1 dout net_2 gnd nmos_vtg w=270.0n l=50.0n
|
||||
M_5 bl en dout vdd pmos_vtg w=720.0n l=50.0n
|
||||
M_6 br en net_1 vdd pmos_vtg w=720.0n l=50.0n
|
||||
M_7 net_2 en gnd gnd nmos_vtg w=270.0n l=50.0n
|
||||
.ENDS sense_amp
|
||||
|
||||
|
||||
.SUBCKT sense_amp_array data[0] bl[0] br[0] data[1] bl[4] br[4] en vdd gnd
|
||||
Xsa_d0 bl[0] br[0] data[0] en vdd gnd sense_amp
|
||||
Xsa_d4 bl[4] br[4] data[1] en vdd gnd sense_amp
|
||||
.ENDS sense_amp_array
|
||||
|
||||
.SUBCKT write_driver din bl br en vdd gnd
|
||||
*inverters for enable and data input
|
||||
minP bl_bar din vdd vdd pmos_vtg w=360.000000n l=50.000000n
|
||||
minN bl_bar din gnd gnd nmos_vtg w=180.000000n l=50.000000n
|
||||
moutP en_bar en vdd vdd pmos_vtg w=360.000000n l=50.000000n
|
||||
moutN en_bar en gnd gnd nmos_vtg w=180.000000n l=50.000000n
|
||||
|
||||
*tristate for BL
|
||||
mout0P int1 bl_bar vdd vdd pmos_vtg w=360.000000n l=50.000000n
|
||||
mout0P2 bl en_bar int1 vdd pmos_vtg w=360.000000n l=50.000000n
|
||||
mout0N bl en int2 gnd nmos_vtg w=180.000000n l=50.000000n
|
||||
mout0N2 int2 bl_bar gnd gnd nmos_vtg w=180.000000n l=50.000000n
|
||||
|
||||
*tristate for BR
|
||||
mout1P int3 din vdd vdd pmos_vtg w=360.000000n l=50.000000n
|
||||
mout1P2 br en_bar int3 vdd pmos_vtg w=360.000000n l=50.000000n
|
||||
mout1N br en int4 gnd nmos_vtg w=180.000000n l=50.000000n
|
||||
mout1N2 int4 din gnd gnd nmos_vtg w=180.000000n l=50.000000n
|
||||
.ENDS write_driver
|
||||
|
||||
|
||||
.SUBCKT write_driver_array data[0] data[1] bl[0] br[0] bl[1] br[1] en vdd gnd
|
||||
XXwrite_driver0 data[0] bl[0] br[0] en vdd gnd write_driver
|
||||
XXwrite_driver4 data[1] bl[1] br[1] en vdd gnd write_driver
|
||||
.ENDS write_driver_array
|
||||
|
||||
.SUBCKT pinv_8 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpinv_nmos Z A gnd gnd nmos_vtg m=1 w=0.09u l=0.05u pd=0.28u ps=0.28u as=0.01125p ad=0.01125p
|
||||
.ENDS pinv_8
|
||||
|
||||
.SUBCKT pnand2_2 A B Z vdd gnd
|
||||
Mpnand2_pmos1 vdd A Z vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpnand2_pmos2 Z B vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpnand2_nmos1 Z B net1 gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.0225p ad=0.0225p
|
||||
Mpnand2_nmos2 net1 A gnd gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.0225p ad=0.0225p
|
||||
.ENDS pnand2_2
|
||||
|
||||
.SUBCKT pnand3_2 A B C Z vdd gnd
|
||||
Mpnand3_pmos1 vdd A Z vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpnand3_pmos2 Z B vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpnand3_pmos3 Z C vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpnand3_nmos1 Z C net1 gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.0225p ad=0.0225p
|
||||
Mpnand3_nmos2 net1 B net2 gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.0225p ad=0.0225p
|
||||
Mpnand3_nmos3 net2 A gnd gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.0225p ad=0.0225p
|
||||
.ENDS pnand3_2
|
||||
|
||||
.SUBCKT pinv_9 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpinv_nmos Z A gnd gnd nmos_vtg m=1 w=0.09u l=0.05u pd=0.28u ps=0.28u as=0.01125p ad=0.01125p
|
||||
.ENDS pinv_9
|
||||
|
||||
.SUBCKT pnand2_3 A B Z vdd gnd
|
||||
Mpnand2_pmos1 vdd A Z vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpnand2_pmos2 Z B vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpnand2_nmos1 Z B net1 gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.0225p ad=0.0225p
|
||||
Mpnand2_nmos2 net1 A gnd gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.0225p ad=0.0225p
|
||||
.ENDS pnand2_3
|
||||
|
||||
.SUBCKT pre2x4 in[0] in[1] out[0] out[1] out[2] out[3] vdd gnd
|
||||
XXpre_inv[0] in[0] inbar[0] vdd gnd pinv_9
|
||||
XXpre_inv[1] in[1] inbar[1] vdd gnd pinv_9
|
||||
XXpre_nand_inv[0] Z[0] out[0] vdd gnd pinv_9
|
||||
XXpre_nand_inv[1] Z[1] out[1] vdd gnd pinv_9
|
||||
XXpre_nand_inv[2] Z[2] out[2] vdd gnd pinv_9
|
||||
XXpre_nand_inv[3] Z[3] out[3] vdd gnd pinv_9
|
||||
XXpre2x4_nand[0] inbar[0] inbar[1] Z[0] vdd gnd pnand2_3
|
||||
XXpre2x4_nand[1] in[0] inbar[1] Z[1] vdd gnd pnand2_3
|
||||
XXpre2x4_nand[2] inbar[0] in[1] Z[2] vdd gnd pnand2_3
|
||||
XXpre2x4_nand[3] in[0] in[1] Z[3] vdd gnd pnand2_3
|
||||
.ENDS pre2x4
|
||||
|
||||
.SUBCKT pinv_10 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpinv_nmos Z A gnd gnd nmos_vtg m=1 w=0.09u l=0.05u pd=0.28u ps=0.28u as=0.01125p ad=0.01125p
|
||||
.ENDS pinv_10
|
||||
|
||||
.SUBCKT pnand3_3 A B C Z vdd gnd
|
||||
Mpnand3_pmos1 vdd A Z vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpnand3_pmos2 Z B vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpnand3_pmos3 Z C vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpnand3_nmos1 Z C net1 gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.0225p ad=0.0225p
|
||||
Mpnand3_nmos2 net1 B net2 gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.0225p ad=0.0225p
|
||||
Mpnand3_nmos3 net2 A gnd gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.0225p ad=0.0225p
|
||||
.ENDS pnand3_3
|
||||
|
||||
.SUBCKT pre3x8 in[0] in[1] in[2] out[0] out[1] out[2] out[3] out[4] out[5] out[6] out[7] vdd gnd
|
||||
XXpre_inv[0] in[0] inbar[0] vdd gnd pinv_10
|
||||
XXpre_inv[1] in[1] inbar[1] vdd gnd pinv_10
|
||||
XXpre_inv[2] in[2] inbar[2] vdd gnd pinv_10
|
||||
XXpre_nand_inv[0] Z[0] out[0] vdd gnd pinv_10
|
||||
XXpre_nand_inv[1] Z[1] out[1] vdd gnd pinv_10
|
||||
XXpre_nand_inv[2] Z[2] out[2] vdd gnd pinv_10
|
||||
XXpre_nand_inv[3] Z[3] out[3] vdd gnd pinv_10
|
||||
XXpre_nand_inv[4] Z[4] out[4] vdd gnd pinv_10
|
||||
XXpre_nand_inv[5] Z[5] out[5] vdd gnd pinv_10
|
||||
XXpre_nand_inv[6] Z[6] out[6] vdd gnd pinv_10
|
||||
XXpre_nand_inv[7] Z[7] out[7] vdd gnd pinv_10
|
||||
XXpre3x8_nand[0] inbar[0] inbar[1] inbar[2] Z[0] vdd gnd pnand3_3
|
||||
XXpre3x8_nand[1] in[0] inbar[1] inbar[2] Z[1] vdd gnd pnand3_3
|
||||
XXpre3x8_nand[2] inbar[0] in[1] inbar[2] Z[2] vdd gnd pnand3_3
|
||||
XXpre3x8_nand[3] in[0] in[1] inbar[2] Z[3] vdd gnd pnand3_3
|
||||
XXpre3x8_nand[4] inbar[0] inbar[1] in[2] Z[4] vdd gnd pnand3_3
|
||||
XXpre3x8_nand[5] in[0] inbar[1] in[2] Z[5] vdd gnd pnand3_3
|
||||
XXpre3x8_nand[6] inbar[0] in[1] in[2] Z[6] vdd gnd pnand3_3
|
||||
XXpre3x8_nand[7] in[0] in[1] in[2] Z[7] vdd gnd pnand3_3
|
||||
.ENDS pre3x8
|
||||
|
||||
.SUBCKT hierarchical_decoder_32rows A[0] A[1] A[2] A[3] A[4] decode[0] decode[1] decode[2] decode[3] decode[4] decode[5] decode[6] decode[7] decode[8] decode[9] decode[10] decode[11] decode[12] decode[13] decode[14] decode[15] decode[16] decode[17] decode[18] decode[19] decode[20] decode[21] decode[22] decode[23] decode[24] decode[25] decode[26] decode[27] decode[28] decode[29] decode[30] decode[31] vdd gnd
|
||||
Xpre[0] A[0] A[1] out[0] out[1] out[2] out[3] vdd gnd pre2x4
|
||||
Xpre3x8[0] A[2] A[3] A[4] out[4] out[5] out[6] out[7] out[8] out[9] out[10] out[11] vdd gnd pre3x8
|
||||
XDEC_NAND[0] out[0] out[4] Z[0] vdd gnd pnand2_2
|
||||
XDEC_NAND[1] out[0] out[5] Z[1] vdd gnd pnand2_2
|
||||
XDEC_NAND[2] out[0] out[6] Z[2] vdd gnd pnand2_2
|
||||
XDEC_NAND[3] out[0] out[7] Z[3] vdd gnd pnand2_2
|
||||
XDEC_NAND[4] out[0] out[8] Z[4] vdd gnd pnand2_2
|
||||
XDEC_NAND[5] out[0] out[9] Z[5] vdd gnd pnand2_2
|
||||
XDEC_NAND[6] out[0] out[10] Z[6] vdd gnd pnand2_2
|
||||
XDEC_NAND[7] out[0] out[11] Z[7] vdd gnd pnand2_2
|
||||
XDEC_NAND[8] out[1] out[4] Z[8] vdd gnd pnand2_2
|
||||
XDEC_NAND[9] out[1] out[5] Z[9] vdd gnd pnand2_2
|
||||
XDEC_NAND[10] out[1] out[6] Z[10] vdd gnd pnand2_2
|
||||
XDEC_NAND[11] out[1] out[7] Z[11] vdd gnd pnand2_2
|
||||
XDEC_NAND[12] out[1] out[8] Z[12] vdd gnd pnand2_2
|
||||
XDEC_NAND[13] out[1] out[9] Z[13] vdd gnd pnand2_2
|
||||
XDEC_NAND[14] out[1] out[10] Z[14] vdd gnd pnand2_2
|
||||
XDEC_NAND[15] out[1] out[11] Z[15] vdd gnd pnand2_2
|
||||
XDEC_NAND[16] out[2] out[4] Z[16] vdd gnd pnand2_2
|
||||
XDEC_NAND[17] out[2] out[5] Z[17] vdd gnd pnand2_2
|
||||
XDEC_NAND[18] out[2] out[6] Z[18] vdd gnd pnand2_2
|
||||
XDEC_NAND[19] out[2] out[7] Z[19] vdd gnd pnand2_2
|
||||
XDEC_NAND[20] out[2] out[8] Z[20] vdd gnd pnand2_2
|
||||
XDEC_NAND[21] out[2] out[9] Z[21] vdd gnd pnand2_2
|
||||
XDEC_NAND[22] out[2] out[10] Z[22] vdd gnd pnand2_2
|
||||
XDEC_NAND[23] out[2] out[11] Z[23] vdd gnd pnand2_2
|
||||
XDEC_NAND[24] out[3] out[4] Z[24] vdd gnd pnand2_2
|
||||
XDEC_NAND[25] out[3] out[5] Z[25] vdd gnd pnand2_2
|
||||
XDEC_NAND[26] out[3] out[6] Z[26] vdd gnd pnand2_2
|
||||
XDEC_NAND[27] out[3] out[7] Z[27] vdd gnd pnand2_2
|
||||
XDEC_NAND[28] out[3] out[8] Z[28] vdd gnd pnand2_2
|
||||
XDEC_NAND[29] out[3] out[9] Z[29] vdd gnd pnand2_2
|
||||
XDEC_NAND[30] out[3] out[10] Z[30] vdd gnd pnand2_2
|
||||
XDEC_NAND[31] out[3] out[11] Z[31] vdd gnd pnand2_2
|
||||
XDEC_INV_[0] Z[0] decode[0] vdd gnd pinv_8
|
||||
XDEC_INV_[1] Z[1] decode[1] vdd gnd pinv_8
|
||||
XDEC_INV_[2] Z[2] decode[2] vdd gnd pinv_8
|
||||
XDEC_INV_[3] Z[3] decode[3] vdd gnd pinv_8
|
||||
XDEC_INV_[4] Z[4] decode[4] vdd gnd pinv_8
|
||||
XDEC_INV_[5] Z[5] decode[5] vdd gnd pinv_8
|
||||
XDEC_INV_[6] Z[6] decode[6] vdd gnd pinv_8
|
||||
XDEC_INV_[7] Z[7] decode[7] vdd gnd pinv_8
|
||||
XDEC_INV_[8] Z[8] decode[8] vdd gnd pinv_8
|
||||
XDEC_INV_[9] Z[9] decode[9] vdd gnd pinv_8
|
||||
XDEC_INV_[10] Z[10] decode[10] vdd gnd pinv_8
|
||||
XDEC_INV_[11] Z[11] decode[11] vdd gnd pinv_8
|
||||
XDEC_INV_[12] Z[12] decode[12] vdd gnd pinv_8
|
||||
XDEC_INV_[13] Z[13] decode[13] vdd gnd pinv_8
|
||||
XDEC_INV_[14] Z[14] decode[14] vdd gnd pinv_8
|
||||
XDEC_INV_[15] Z[15] decode[15] vdd gnd pinv_8
|
||||
XDEC_INV_[16] Z[16] decode[16] vdd gnd pinv_8
|
||||
XDEC_INV_[17] Z[17] decode[17] vdd gnd pinv_8
|
||||
XDEC_INV_[18] Z[18] decode[18] vdd gnd pinv_8
|
||||
XDEC_INV_[19] Z[19] decode[19] vdd gnd pinv_8
|
||||
XDEC_INV_[20] Z[20] decode[20] vdd gnd pinv_8
|
||||
XDEC_INV_[21] Z[21] decode[21] vdd gnd pinv_8
|
||||
XDEC_INV_[22] Z[22] decode[22] vdd gnd pinv_8
|
||||
XDEC_INV_[23] Z[23] decode[23] vdd gnd pinv_8
|
||||
XDEC_INV_[24] Z[24] decode[24] vdd gnd pinv_8
|
||||
XDEC_INV_[25] Z[25] decode[25] vdd gnd pinv_8
|
||||
XDEC_INV_[26] Z[26] decode[26] vdd gnd pinv_8
|
||||
XDEC_INV_[27] Z[27] decode[27] vdd gnd pinv_8
|
||||
XDEC_INV_[28] Z[28] decode[28] vdd gnd pinv_8
|
||||
XDEC_INV_[29] Z[29] decode[29] vdd gnd pinv_8
|
||||
XDEC_INV_[30] Z[30] decode[30] vdd gnd pinv_8
|
||||
XDEC_INV_[31] Z[31] decode[31] vdd gnd pinv_8
|
||||
.ENDS hierarchical_decoder_32rows
|
||||
|
||||
.SUBCKT msf_address din[0] din[1] din[2] din[3] din[4] din[5] din[6] dout[0] dout_bar[0] dout[1] dout_bar[1] dout[2] dout_bar[2] dout[3] dout_bar[3] dout[4] dout_bar[4] dout[5] dout_bar[5] dout[6] dout_bar[6] clk vdd gnd
|
||||
XXdff0 din[0] dout[0] dout_bar[0] clk vdd gnd ms_flop
|
||||
XXdff1 din[1] dout[1] dout_bar[1] clk vdd gnd ms_flop
|
||||
XXdff2 din[2] dout[2] dout_bar[2] clk vdd gnd ms_flop
|
||||
XXdff3 din[3] dout[3] dout_bar[3] clk vdd gnd ms_flop
|
||||
XXdff4 din[4] dout[4] dout_bar[4] clk vdd gnd ms_flop
|
||||
XXdff5 din[5] dout[5] dout_bar[5] clk vdd gnd ms_flop
|
||||
XXdff6 din[6] dout[6] dout_bar[6] clk vdd gnd ms_flop
|
||||
.ENDS msf_address
|
||||
|
||||
.SUBCKT msf_data_in din[0] din[1] dout[0] dout_bar[0] dout[1] dout_bar[1] clk vdd gnd
|
||||
XXdff0 din[0] dout[0] dout_bar[0] clk vdd gnd ms_flop
|
||||
XXdff4 din[1] dout[1] dout_bar[1] clk vdd gnd ms_flop
|
||||
.ENDS msf_data_in
|
||||
|
||||
.SUBCKT tri_gate in out en en_bar vdd gnd
|
||||
M_1 net_2 in_inv gnd gnd NMOS_VTG W=180.000000n L=50.000000n
|
||||
M_2 out en net_2 gnd NMOS_VTG W=180.000000n L=50.000000n
|
||||
M_3 net_3 in_inv vdd vdd PMOS_VTG W=360.000000n L=50.000000n
|
||||
M_4 out en_bar net_3 vdd PMOS_VTG W=360.000000n L=50.000000n
|
||||
M_5 in_inv in vdd vdd PMOS_VTG W=180.000000n L=50.000000n
|
||||
M_6 in_inv in gnd gnd NMOS_VTG W=90.000000n L=50.000000n
|
||||
.ENDS
|
||||
|
||||
|
||||
.SUBCKT tri_gate_array in[0] in[1] out[0] out[1] en en_bar vdd gnd
|
||||
XXtri_gate0 in[0] out[0] en en_bar vdd gnd tri_gate
|
||||
XXtri_gate4 in[1] out[1] en en_bar vdd gnd tri_gate
|
||||
.ENDS tri_gate_array
|
||||
|
||||
.SUBCKT pinv_11 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpinv_nmos Z A gnd gnd nmos_vtg m=1 w=0.09u l=0.05u pd=0.28u ps=0.28u as=0.01125p ad=0.01125p
|
||||
.ENDS pinv_11
|
||||
|
||||
.SUBCKT pinv_12 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpinv_nmos Z A gnd gnd nmos_vtg m=1 w=0.09u l=0.05u pd=0.28u ps=0.28u as=0.01125p ad=0.01125p
|
||||
.ENDS pinv_12
|
||||
|
||||
.SUBCKT pnand2_4 A B Z vdd gnd
|
||||
Mpnand2_pmos1 vdd A Z vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpnand2_pmos2 Z B vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpnand2_nmos1 Z B net1 gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.0225p ad=0.0225p
|
||||
Mpnand2_nmos2 net1 A gnd gnd nmos_vtg m=1 w=0.18u l=0.05u pd=0.46u ps=0.46u as=0.0225p ad=0.0225p
|
||||
.ENDS pnand2_4
|
||||
|
||||
.SUBCKT wordline_driver in[0] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[19] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] in[29] in[30] in[31] wl[0] wl[1] wl[2] wl[3] wl[4] wl[5] wl[6] wl[7] wl[8] wl[9] wl[10] wl[11] wl[12] wl[13] wl[14] wl[15] wl[16] wl[17] wl[18] wl[19] wl[20] wl[21] wl[22] wl[23] wl[24] wl[25] wl[26] wl[27] wl[28] wl[29] wl[30] wl[31] en vdd gnd
|
||||
Xwl_driver_inv_en0 en en_bar[0] vdd gnd pinv_12
|
||||
Xwl_driver_nand0 en_bar[0] in[0] net[0] vdd gnd pnand2_4
|
||||
Xwl_driver_inv0 net[0] wl[0] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en1 en en_bar[1] vdd gnd pinv_12
|
||||
Xwl_driver_nand1 en_bar[1] in[1] net[1] vdd gnd pnand2_4
|
||||
Xwl_driver_inv1 net[1] wl[1] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en2 en en_bar[2] vdd gnd pinv_12
|
||||
Xwl_driver_nand2 en_bar[2] in[2] net[2] vdd gnd pnand2_4
|
||||
Xwl_driver_inv2 net[2] wl[2] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en3 en en_bar[3] vdd gnd pinv_12
|
||||
Xwl_driver_nand3 en_bar[3] in[3] net[3] vdd gnd pnand2_4
|
||||
Xwl_driver_inv3 net[3] wl[3] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en4 en en_bar[4] vdd gnd pinv_12
|
||||
Xwl_driver_nand4 en_bar[4] in[4] net[4] vdd gnd pnand2_4
|
||||
Xwl_driver_inv4 net[4] wl[4] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en5 en en_bar[5] vdd gnd pinv_12
|
||||
Xwl_driver_nand5 en_bar[5] in[5] net[5] vdd gnd pnand2_4
|
||||
Xwl_driver_inv5 net[5] wl[5] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en6 en en_bar[6] vdd gnd pinv_12
|
||||
Xwl_driver_nand6 en_bar[6] in[6] net[6] vdd gnd pnand2_4
|
||||
Xwl_driver_inv6 net[6] wl[6] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en7 en en_bar[7] vdd gnd pinv_12
|
||||
Xwl_driver_nand7 en_bar[7] in[7] net[7] vdd gnd pnand2_4
|
||||
Xwl_driver_inv7 net[7] wl[7] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en8 en en_bar[8] vdd gnd pinv_12
|
||||
Xwl_driver_nand8 en_bar[8] in[8] net[8] vdd gnd pnand2_4
|
||||
Xwl_driver_inv8 net[8] wl[8] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en9 en en_bar[9] vdd gnd pinv_12
|
||||
Xwl_driver_nand9 en_bar[9] in[9] net[9] vdd gnd pnand2_4
|
||||
Xwl_driver_inv9 net[9] wl[9] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en10 en en_bar[10] vdd gnd pinv_12
|
||||
Xwl_driver_nand10 en_bar[10] in[10] net[10] vdd gnd pnand2_4
|
||||
Xwl_driver_inv10 net[10] wl[10] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en11 en en_bar[11] vdd gnd pinv_12
|
||||
Xwl_driver_nand11 en_bar[11] in[11] net[11] vdd gnd pnand2_4
|
||||
Xwl_driver_inv11 net[11] wl[11] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en12 en en_bar[12] vdd gnd pinv_12
|
||||
Xwl_driver_nand12 en_bar[12] in[12] net[12] vdd gnd pnand2_4
|
||||
Xwl_driver_inv12 net[12] wl[12] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en13 en en_bar[13] vdd gnd pinv_12
|
||||
Xwl_driver_nand13 en_bar[13] in[13] net[13] vdd gnd pnand2_4
|
||||
Xwl_driver_inv13 net[13] wl[13] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en14 en en_bar[14] vdd gnd pinv_12
|
||||
Xwl_driver_nand14 en_bar[14] in[14] net[14] vdd gnd pnand2_4
|
||||
Xwl_driver_inv14 net[14] wl[14] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en15 en en_bar[15] vdd gnd pinv_12
|
||||
Xwl_driver_nand15 en_bar[15] in[15] net[15] vdd gnd pnand2_4
|
||||
Xwl_driver_inv15 net[15] wl[15] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en16 en en_bar[16] vdd gnd pinv_12
|
||||
Xwl_driver_nand16 en_bar[16] in[16] net[16] vdd gnd pnand2_4
|
||||
Xwl_driver_inv16 net[16] wl[16] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en17 en en_bar[17] vdd gnd pinv_12
|
||||
Xwl_driver_nand17 en_bar[17] in[17] net[17] vdd gnd pnand2_4
|
||||
Xwl_driver_inv17 net[17] wl[17] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en18 en en_bar[18] vdd gnd pinv_12
|
||||
Xwl_driver_nand18 en_bar[18] in[18] net[18] vdd gnd pnand2_4
|
||||
Xwl_driver_inv18 net[18] wl[18] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en19 en en_bar[19] vdd gnd pinv_12
|
||||
Xwl_driver_nand19 en_bar[19] in[19] net[19] vdd gnd pnand2_4
|
||||
Xwl_driver_inv19 net[19] wl[19] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en20 en en_bar[20] vdd gnd pinv_12
|
||||
Xwl_driver_nand20 en_bar[20] in[20] net[20] vdd gnd pnand2_4
|
||||
Xwl_driver_inv20 net[20] wl[20] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en21 en en_bar[21] vdd gnd pinv_12
|
||||
Xwl_driver_nand21 en_bar[21] in[21] net[21] vdd gnd pnand2_4
|
||||
Xwl_driver_inv21 net[21] wl[21] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en22 en en_bar[22] vdd gnd pinv_12
|
||||
Xwl_driver_nand22 en_bar[22] in[22] net[22] vdd gnd pnand2_4
|
||||
Xwl_driver_inv22 net[22] wl[22] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en23 en en_bar[23] vdd gnd pinv_12
|
||||
Xwl_driver_nand23 en_bar[23] in[23] net[23] vdd gnd pnand2_4
|
||||
Xwl_driver_inv23 net[23] wl[23] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en24 en en_bar[24] vdd gnd pinv_12
|
||||
Xwl_driver_nand24 en_bar[24] in[24] net[24] vdd gnd pnand2_4
|
||||
Xwl_driver_inv24 net[24] wl[24] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en25 en en_bar[25] vdd gnd pinv_12
|
||||
Xwl_driver_nand25 en_bar[25] in[25] net[25] vdd gnd pnand2_4
|
||||
Xwl_driver_inv25 net[25] wl[25] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en26 en en_bar[26] vdd gnd pinv_12
|
||||
Xwl_driver_nand26 en_bar[26] in[26] net[26] vdd gnd pnand2_4
|
||||
Xwl_driver_inv26 net[26] wl[26] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en27 en en_bar[27] vdd gnd pinv_12
|
||||
Xwl_driver_nand27 en_bar[27] in[27] net[27] vdd gnd pnand2_4
|
||||
Xwl_driver_inv27 net[27] wl[27] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en28 en en_bar[28] vdd gnd pinv_12
|
||||
Xwl_driver_nand28 en_bar[28] in[28] net[28] vdd gnd pnand2_4
|
||||
Xwl_driver_inv28 net[28] wl[28] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en29 en en_bar[29] vdd gnd pinv_12
|
||||
Xwl_driver_nand29 en_bar[29] in[29] net[29] vdd gnd pnand2_4
|
||||
Xwl_driver_inv29 net[29] wl[29] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en30 en en_bar[30] vdd gnd pinv_12
|
||||
Xwl_driver_nand30 en_bar[30] in[30] net[30] vdd gnd pnand2_4
|
||||
Xwl_driver_inv30 net[30] wl[30] vdd gnd pinv_11
|
||||
Xwl_driver_inv_en31 en en_bar[31] vdd gnd pinv_12
|
||||
Xwl_driver_nand31 en_bar[31] in[31] net[31] vdd gnd pnand2_4
|
||||
Xwl_driver_inv31 net[31] wl[31] vdd gnd pinv_11
|
||||
.ENDS wordline_driver
|
||||
|
||||
.SUBCKT pinv_13 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd pmos_vtg m=1 w=0.27u l=0.05u pd=0.64u ps=0.64u as=0.03375p ad=0.03375p
|
||||
Mpinv_nmos Z A gnd gnd nmos_vtg m=1 w=0.09u l=0.05u pd=0.28u ps=0.28u as=0.01125p ad=0.01125p
|
||||
.ENDS pinv_13
|
||||
|
||||
.SUBCKT bank DATA[0] DATA[1] ADDR[0] ADDR[1] ADDR[2] ADDR[3] ADDR[4] ADDR[5] ADDR[6] s_en w_en tri_en_bar tri_en clk_bar clk_buf vdd gnd
|
||||
Xbitcell_array bl[0] br[0] bl[1] br[1] bl[2] br[2] bl[3] br[3] bl[4] br[4] bl[5] br[5] bl[6] br[6] bl[7] br[7] wl[0] wl[1] wl[2] wl[3] wl[4] wl[5] wl[6] wl[7] wl[8] wl[9] wl[10] wl[11] wl[12] wl[13] wl[14] wl[15] wl[16] wl[17] wl[18] wl[19] wl[20] wl[21] wl[22] wl[23] wl[24] wl[25] wl[26] wl[27] wl[28] wl[29] wl[30] wl[31] vdd gnd bitcell_array
|
||||
Xprecharge_array bl[0] br[0] bl[1] br[1] bl[2] br[2] bl[3] br[3] bl[4] br[4] bl[5] br[5] bl[6] br[6] bl[7] br[7] clk_bar vdd precharge_array
|
||||
Xcolumn_mux_array bl[0] br[0] bl[1] br[1] bl[2] br[2] bl[3] br[3] bl[4] br[4] bl[5] br[5] bl[6] br[6] bl[7] br[7] sel[0] sel[1] sel[2] sel[3] bl_out[0] br_out[0] bl_out[1] br_out[1] gnd columnmux_array
|
||||
Xcol_address_decoder A[5] A[6] sel[0] sel[1] sel[2] sel[3] vdd gnd pre2x4
|
||||
Xsense_amp_array data_out[0] bl_out[0] br_out[0] data_out[1] bl_out[1] br_out[1] s_en vdd gnd sense_amp_array
|
||||
Xwrite_driver_array data_in[0] data_in[1] bl_out[0] br_out[0] bl_out[1] br_out[1] w_en vdd gnd write_driver_array
|
||||
Xdata_in_flop_array DATA[0] DATA[1] data_in[0] data_in_bar[0] data_in[1] data_in_bar[1] clk_bar vdd gnd msf_data_in
|
||||
Xtri_gate_array data_out[0] data_out[1] DATA[0] DATA[1] tri_en tri_en_bar vdd gnd tri_gate_array
|
||||
Xrow_decoder A[0] A[1] A[2] A[3] A[4] dec_out[0] dec_out[1] dec_out[2] dec_out[3] dec_out[4] dec_out[5] dec_out[6] dec_out[7] dec_out[8] dec_out[9] dec_out[10] dec_out[11] dec_out[12] dec_out[13] dec_out[14] dec_out[15] dec_out[16] dec_out[17] dec_out[18] dec_out[19] dec_out[20] dec_out[21] dec_out[22] dec_out[23] dec_out[24] dec_out[25] dec_out[26] dec_out[27] dec_out[28] dec_out[29] dec_out[30] dec_out[31] vdd gnd hierarchical_decoder_32rows
|
||||
Xwordline_driver dec_out[0] dec_out[1] dec_out[2] dec_out[3] dec_out[4] dec_out[5] dec_out[6] dec_out[7] dec_out[8] dec_out[9] dec_out[10] dec_out[11] dec_out[12] dec_out[13] dec_out[14] dec_out[15] dec_out[16] dec_out[17] dec_out[18] dec_out[19] dec_out[20] dec_out[21] dec_out[22] dec_out[23] dec_out[24] dec_out[25] dec_out[26] dec_out[27] dec_out[28] dec_out[29] dec_out[30] dec_out[31] wl[0] wl[1] wl[2] wl[3] wl[4] wl[5] wl[6] wl[7] wl[8] wl[9] wl[10] wl[11] wl[12] wl[13] wl[14] wl[15] wl[16] wl[17] wl[18] wl[19] wl[20] wl[21] wl[22] wl[23] wl[24] wl[25] wl[26] wl[27] wl[28] wl[29] wl[30] wl[31] clk_buf vdd gnd wordline_driver
|
||||
Xaddress_flop_array ADDR[0] ADDR[1] ADDR[2] ADDR[3] ADDR[4] ADDR[5] ADDR[6] A[0] A_bar[0] A[1] A_bar[1] A[2] A_bar[2] A[3] A_bar[3] A[4] A_bar[4] A[5] A_bar[5] A[6] A_bar[6] clk_buf vdd gnd msf_address
|
||||
.ENDS bank
|
||||
|
||||
.SUBCKT sram_2_16_1_freepdk45 DATA[0] DATA[1] ADDR[0] ADDR[1] ADDR[2] ADDR[3] ADDR[4] ADDR[5] ADDR[6] CSb WEb OEb clk vdd gnd
|
||||
Xbank0 DATA[0] DATA[1] ADDR[0] ADDR[1] ADDR[2] ADDR[3] ADDR[4] ADDR[5] ADDR[6] s_en w_en tri_en_bar tri_en clk_bar clk_buf vdd gnd bank
|
||||
Xcontrol CSb WEb OEb clk s_en w_en tri_en tri_en_bar clk_bar clk_buf vdd gnd control_logic
|
||||
.ENDS sram_2_16_1_freepdk45
|
||||
|
|
@ -1,47 +0,0 @@
|
|||
// OpenRAM SRAM model
|
||||
// Words: 128
|
||||
// Word size: 2
|
||||
|
||||
module sram_2_16_1_freepdk45(DATA,ADDR,CSb,WEb,OEb,clk);
|
||||
|
||||
parameter DATA_WIDTH = 2 ;
|
||||
parameter ADDR_WIDTH = 7 ;
|
||||
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
|
||||
parameter DELAY = 3 ;
|
||||
|
||||
inout [DATA_WIDTH-1:0] DATA;
|
||||
input [ADDR_WIDTH-1:0] ADDR;
|
||||
input CSb; // active low chip select
|
||||
input WEb; // active low write control
|
||||
input OEb; // active output enable
|
||||
input clk; // clock
|
||||
|
||||
reg [DATA_WIDTH-1:0] data_out ;
|
||||
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
|
||||
|
||||
// Tri-State Buffer control
|
||||
// output : When WEb = 1, oeb = 0, csb = 0
|
||||
assign DATA = (!CSb && !OEb && WEb) ? data_out : 2'bz;
|
||||
|
||||
// Memory Write Block
|
||||
// Write Operation : When WEb = 0, CSb = 0
|
||||
always @ (posedge clk)
|
||||
begin : MEM_WRITE
|
||||
if ( !CSb && !WEb ) begin
|
||||
mem[ADDR] = DATA;
|
||||
$display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA);
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// Memory Read Block
|
||||
// Read Operation : When WEb = 1, CSb = 0
|
||||
always @ (posedge clk)
|
||||
begin : MEM_READ
|
||||
if (!CSb && WEb) begin
|
||||
data_out <= #(DELAY) mem[ADDR];
|
||||
$display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]);
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,329 +0,0 @@
|
|||
library (sram_2_16_1_freepdk45_TT_10V_25C_lib){
|
||||
delay_model : "table_lookup";
|
||||
time_unit : "1ns" ;
|
||||
voltage_unit : "1v" ;
|
||||
current_unit : "1mA" ;
|
||||
resistance_unit : "1kohm" ;
|
||||
capacitive_load_unit(1 ,fF) ;
|
||||
leakage_power_unit : "1mW" ;
|
||||
pulling_resistance_unit :"1kohm" ;
|
||||
operating_conditions(TT){
|
||||
voltage : 1.0 ;
|
||||
temperature : 25;
|
||||
}
|
||||
|
||||
input_threshold_pct_fall : 50.0 ;
|
||||
output_threshold_pct_fall : 50.0 ;
|
||||
input_threshold_pct_rise : 50.0 ;
|
||||
output_threshold_pct_rise : 50.0 ;
|
||||
slew_lower_threshold_pct_fall : 10.0 ;
|
||||
slew_upper_threshold_pct_fall : 90.0 ;
|
||||
slew_lower_threshold_pct_rise : 10.0 ;
|
||||
slew_upper_threshold_pct_rise : 90.0 ;
|
||||
|
||||
default_cell_leakage_power : 0.0 ;
|
||||
default_leakage_power_density : 0.0 ;
|
||||
default_input_pin_cap : 1.0 ;
|
||||
default_inout_pin_cap : 1.0 ;
|
||||
default_output_pin_cap : 0.0 ;
|
||||
default_max_transition : 0.5 ;
|
||||
default_fanout_load : 1.0 ;
|
||||
default_max_fanout : 4.0 ;
|
||||
default_connection_class : universal ;
|
||||
|
||||
lu_table_template(CELL_TABLE){
|
||||
variable_1 : input_net_transition;
|
||||
variable_2 : total_output_net_capacitance;
|
||||
index_1("0.00125, 0.005, 0.04");
|
||||
index_2("0.052275, 0.2091, 1.6728");
|
||||
}
|
||||
|
||||
lu_table_template(CONSTRAINT_TABLE){
|
||||
variable_1 : related_pin_transition;
|
||||
variable_2 : constrained_pin_transition;
|
||||
index_1("0.00125, 0.005, 0.04");
|
||||
index_2("0.00125, 0.005, 0.04");
|
||||
}
|
||||
|
||||
default_operating_conditions : TT;
|
||||
|
||||
|
||||
type (DATA){
|
||||
base_type : array;
|
||||
data_type : bit;
|
||||
bit_width : 2;
|
||||
bit_from : 0;
|
||||
bit_to : 1;
|
||||
}
|
||||
|
||||
type (ADDR){
|
||||
base_type : array;
|
||||
data_type : bit;
|
||||
bit_width : 7;
|
||||
bit_from : 0;
|
||||
bit_to : 6;
|
||||
}
|
||||
|
||||
cell (sram_2_16_1_freepdk45){
|
||||
memory(){
|
||||
type : ram;
|
||||
address_width : 7;
|
||||
word_width : 2;
|
||||
}
|
||||
interface_timing : true;
|
||||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 1756.7563625;
|
||||
|
||||
bus(DATA){
|
||||
bus_type : DATA;
|
||||
direction : inout;
|
||||
max_capacitance : 1.6728;
|
||||
three_state : "!OEb & !clk";
|
||||
memory_write(){
|
||||
address : ADDR;
|
||||
clocked_on : clk;
|
||||
}
|
||||
memory_read(){
|
||||
address : ADDR;
|
||||
}
|
||||
pin(DATA[1:0]){
|
||||
internal_power(){
|
||||
when : "OEb & !clk";
|
||||
rise_power(scalar){
|
||||
values("Power Data: Dynamic 174266.64, Leakage 423.0 in nW");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("Power Data: Dynamic 174266.64, Leakage 423.0 in nW");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!OEb & !clk";
|
||||
rise_power(scalar){
|
||||
values("Power Data: Dynamic 174266.64, Leakage 423.0 in nW");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("Power Data: Dynamic 174266.64, Leakage 423.0 in nW");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk";
|
||||
timing_type : falling_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.167, 0.168, 0.177",\
|
||||
"0.167, 0.168, 0.177",\
|
||||
"0.167, 0.168, 0.177");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("0.167, 0.168, 0.177",\
|
||||
"0.167, 0.168, 0.177",\
|
||||
"0.167, 0.168, 0.177");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.006, 0.007, 0.018",\
|
||||
"0.006, 0.007, 0.018",\
|
||||
"0.006, 0.007, 0.018");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.006, 0.007, 0.018",\
|
||||
"0.006, 0.007, 0.018",\
|
||||
"0.006, 0.007, 0.018");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bus(ADDR){
|
||||
bus_type : ADDR;
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
max_transition : 0.04;
|
||||
fanout_load : 1.000000;
|
||||
pin(ADDR[6:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(CSb){
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(OEb){
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(WEb){
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(clk){
|
||||
clock : true;
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk;
|
||||
rise_constraint(scalar) {
|
||||
values("0.0");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.0");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk;
|
||||
rise_constraint(scalar) {
|
||||
values("0.0");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.0");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -275,13 +275,21 @@ spice["msflop_delay"] = 20.5 # DFF Clk-to-q delay in ps
|
|||
spice["msflop_slew"] = 13.1 # DFF output slew in ps w/ no load
|
||||
spice["msflop_in_cap"] = 0.2091 # Input capacitance of ms_flop (Din) [Femto-farad]
|
||||
|
||||
# analytical power parameters
|
||||
spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nano-Watts
|
||||
spice["inv_leakage"] = 1 # Leakage power of inverter, temporary until a way to calculate is determined, in nW
|
||||
spice["msflop_power"] = 1 # Total power of a single flop in nano-Watts
|
||||
# analytical power parameters, many values are temporary
|
||||
spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW
|
||||
spice["inv_leakage"] = 1 # Leakage power of inverter in nW
|
||||
spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW
|
||||
spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW
|
||||
spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW
|
||||
spice["msflop_leakage"] = 1 # Leakage power of flop in nW
|
||||
spice["flop_para_cap"] = 2 # Parasitic Output capacitance in fF
|
||||
|
||||
spice["default_event_rate"] = 200 # Default event activity of every gate. Temporary value. In Mega-Hz
|
||||
spice["inv_transisition_prob"] = .5 # Transition probability of inverter. Will be dynamically calculated later.
|
||||
spice["default_event_rate"] = 100 # Default event activity of every gate. MHz
|
||||
spice["flop_transisition_prob"] = .5 # Transition probability of inverter.
|
||||
spice["inv_transisition_prob"] = .5 # Transition probability of inverter.
|
||||
spice["nand2_transisition_prob"] = .1875 # Transition probability of 2-input nand.
|
||||
spice["nand3_transisition_prob"] = .1094 # Transition probability of 3-input nand.
|
||||
spice["nor2_transisition_prob"] = .1875 # Transition probability of 2-input nor.
|
||||
|
||||
###################################################
|
||||
##END Spice Simulation Parameters
|
||||
|
|
|
|||
Loading…
Reference in New Issue