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First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.

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This commit is contained in:
Hunter Nichols
2018-02-26 16:32:28 -08:00
parent 62ad30e741
commit d0e6dc9ce7
29 changed files with 107 additions and 12945 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/bank.py
-19
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@@ -1229,22 +1229,3 @@ class bank(design.design):
+ bitcell_array_delay + bl_t_data_out_delay + data_t_DATA_delay
return result
# def analytical_power(self, slew, load):
# """ return analytical power of the bank. Basic skeleton code"""
# msf_addr_power = self.msf_address.analytical_power(slew, self.decoder.input_load())
# msf_data_in_power = self.msf_data_in.analytical_power(slew, self.decoder.input_load())
# decoder_power = self.decoder.analytical_power(slew, load)
# word_driver_power = self.wordline_driver.analytical_power(slew, self.bitcell_array.input_load())
# bitcell_array_power = self.bitcell_array.analytical_power(slew)
# bl_t_data_out_power = self.sense_amp_array.analytical_power(slew,
# self.bitcell_array.output_load())
# data_t_DATA_power = self.tri_gate_array.analytical_power(slew, load)
# total_power = msf_addr_power + msf_data_in_power + decoder_power + word_driver_power \
# + bitcell_array_power + bl_t_data_out_power + data_t_DATA_power
# return total_power
compiler/modules/bitcell.py
+1 -1
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@@ -35,7 +35,7 @@ class bitcell(design.design):
result = self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew, swing = swing)
return result
def analytical_power(self, vdd, temp, load):
def analytical_power(self, proc, vdd, temp, load):
#Power of the bitcell. Mostly known for leakage, but dynamic can also be factored in.
#Only consider leakage power for now. Value defined in tech file rather than calculated.
from tech import spice
compiler/modules/bitcell_array.py
+10 -10
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@@ -178,27 +178,27 @@ class bitcell_array(design.design):
return self.return_delay(cell_delay.delay+wl_to_cell_delay.delay,
wl_to_cell_delay.slew)
def analytical_power(self, vdd, temp, load):
def analytical_power(self, proc, vdd, temp, load):
#This will be pretty bare bones as the power needs to be determined from the dynamic power
#of the word line, leakage power from the cell, and dynamic power of the bitlines as a few
#sources for power. These features are tbd.
from tech import drc
#calculate wl dynamic power, functions not implemented.
#wl_wire = self.gen_wl_wire()
#wl_to_cell_power = wl_wire.return_power_over_wire(slew)
# hypothetical delay from cell to bl end without sense amp
# Dynamic Power from Bitline
bl_wire = self.gen_bl_wire()
cell_load = 2 * bl_wire.return_input_cap() # we ingore the wire r
# hence just use the whole c
bl_swing = 0.1
cell_load = 2 * bl_wire.return_input_cap()
bl_swing = 0.1 #This should probably be defined in the tech file
freq = spice["default_event_rate"]
bitline_dynamic = bl_swing*cell_load*vdd*vdd*freq #not sure if calculation is correct
#Calculate the bitcell power which can include leakage as well as bitline dynamic
cell_power = self.cell.analytical_power(vdd, temp, load)
cell_power = self.cell.analytical_power(proc, vdd, temp, load)
#Leakage power grows with entire array. Dynamic currently not accounted for.
total_power = self.return_power(cell_power.dynamic, cell_power.leakage * self.column_size * self.row_size)
#calculate power for entire array based off a single cell
total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
cell_power.leakage * self.column_size * self.row_size)
return total_power
def gen_wl_wire(self):
compiler/modules/control_logic.py
+1 -11
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@@ -687,14 +687,4 @@ class control_logic(design.design):
height=pin.height(),
width=pin.width())
def analytical_power(self, vdd, temp, load):
#This has yet to be fully determined.
print "Instances:"
total_power = self.return_power() #empty power object
for inst in self.insts:
print inst.name," Instance"
total_power += inst.mod.analytical_power(vdd, temp, load)
#currently, only return flop array power
return total_power
compiler/modules/hierarchical_decoder.py
-15
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@@ -494,21 +494,6 @@ class hierarchical_decoder(design.design):
result = result + z_t_decodeout_delay
return result
# def analytical_power(self, slew, load = 0.0):
# # A -> out
# if self.determine_predecodes(self.num_inputs)[1]==0:
# pre = self.pre2_4
# nand = self.nand2
# else:
# pre = self.pre3_8
# nand = self.nand3
# a_t_out_power = pre.analytical_power(slew=slew,load = nand.input_load())
# out_t_z_power = nand.analytical_power(slew,
# load = self.inv.input_load())
# z_t_decodeout_power = self.inv.analytical_power(slew, load = load)
# return a_t_out_power + out_t_z_power + z_t_decodeout_power
def input_load(self):
if self.determine_predecodes(self.num_inputs)[1]==0:
compiler/modules/hierarchical_predecode2x4.py
-11
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@@ -55,17 +55,6 @@ class hierarchical_predecode2x4(hierarchical_predecode):
return a_t_b_delay + b_t_z_delay + a_t_out_delay
# def analytical_power(self, slew, load = 0.0 ):
# # in -> inbar
# a_t_b_power = self.inv.analytical_power(slew=slew, load=self.nand.input_load())
# # inbar -> z
# b_t_z_power = self.nand.analytical_power(slew, load=self.inv.input_load())
# # Z -> out
# a_t_out_power = self.inv.analytical_power(slew, load=load)
# return a_t_b_power + b_t_z_power + a_t_out_power
def input_load(self):
return self.nand.input_load()
compiler/modules/hierarchical_predecode3x8.py
-11
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@@ -63,17 +63,6 @@ class hierarchical_predecode3x8(hierarchical_predecode):
return a_t_b_delay + b_t_z_delay + a_t_out_delay
# def analytical_power(self, slew, load = 0.0 ):
# # in -> inbar
# a_t_b_power = self.inv.analytical_power(slew=slew, load=self.nand.input_load())
# # inbar -> z
# b_t_z_power = self.nand.analytical_power(slew, load=self.inv.input_load())
# # Z -> out
# a_t_out_power = self.inv.analytical_power(slew, load=load)
# return a_t_b_power + b_t_z_power + a_t_out_power
def input_load(self):
return self.nand.input_load()
compiler/modules/ms_flop.py
+16 -4
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@@ -27,11 +27,23 @@ class ms_flop(design.design):
result = self.return_delay(spice["msflop_delay"], spice["msflop_slew"])
return result
def analytical_power(self, vdd, temp, load):
#Value taken from tech file.
def analytical_power(self, proc, vdd, temp, load):
#Returns dynamic and leakage power. Results in nW
from tech import spice
return self.return_power()
#return spice["msflop_power"]
c_eff = self.calculate_effective_capacitance(load)
f = spice["default_event_rate"]
power_dyn = c_eff*vdd*vdd*f
power_leak = spice["nor2_leakage"]
total_power = self.return_power(power_dyn, power_leak)
return total_power
def calculate_effective_capacitance(self, load):
from tech import spice, parameter
c_load = load
c_para = spice["flop_para_cap"]#ff
transistion_prob = spice["flop_transisition_prob"]
return transistion_prob*(c_load + c_para)
compiler/modules/ms_flop_array.py
-2
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@@ -135,5 +135,3 @@ class ms_flop_array(design.design):
def analytical_delay(self, slew, load=0.0):
return self.ms.analytical_delay(slew=slew, load=load)
# def analytical_power(self, vdd, temp, load):
# return self.columns * self.ms.analytical_power(slew=slew, load=load)
compiler/modules/replica_bitline.py
-12
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@@ -344,15 +344,3 @@ class replica_bitline(design.design):
height=pin.height(),
width=pin.width())
# def analytical_power(self, vdd, temp, load):
# #This has yet to be fully determined.
# print self.name," Instances:"
# total_power = self.return_power()
# for inst in self.insts:
# print inst.name," Instance"
# total_power += inst.mod.analytical_power(vdd, temp, load)
# print self.name," Instances End"
# #currently, only return flop array power
# return total_power
compiler/modules/sense_amp.py
+1 -1
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@@ -30,7 +30,7 @@ class sense_amp(design.design):
result = self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew)
return self.return_delay(result.delay, result.slew)
def analytical_power(self, vdd, temp, load):
def analytical_power(self, proc, vdd, temp, load):
#Not sure how to determine this yet. Sense amps return zero power for now
total_power = self.return_power()
return total_power
compiler/modules/sense_amp_array.py
-2
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@@ -118,5 +118,3 @@ class sense_amp_array(design.design):
def analytical_delay(self, slew, load=0.0):
return self.amp.analytical_delay(slew=slew, load=load)
# def analytical_power(self, slew, load=0.0):
# return self.amp.analytical_power(slew=slew, load=load)
compiler/modules/tri_gate.py
+1 -1
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@@ -33,7 +33,7 @@ class tri_gate(design.design):
c_para = spice["min_tx_drain_c"]
return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew)
def analytical_power(self, vdd, temp, load):
def analytical_power(self, proc, vdd, temp, load):
#Not sure how to determine this yet. Tri-gates return zero power for now
total_power = self.return_power()
return total_power
compiler/modules/tri_gate_array.py
-2
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@@ -112,5 +112,3 @@ class tri_gate_array(design.design):
def analytical_delay(self, slew, load=0.0):
return self.tri.analytical_delay(slew = slew, load = load)
# def analytical_power(self, slew, load=0.0):
# return self.tri.analytical_power(slew = slew, load = load)
compiler/modules/wordline_driver.py
-8
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@@ -205,15 +205,7 @@ class wordline_driver(design.design):
net_t_wl = self.inv.analytical_delay(decode_t_net.slew, load)
return decode_t_net + net_t_wl
# def analytical_power(self, slew, load=0):
# # decode -> net
# decode_p_net = self.nand2.analytical_power(slew, self.inv.input_load())
# # net -> wl
# net_p_wl = self.inv.analytical_power(slew, load)
# return decode_p_net + net_p_wl
def input_load(self):
return self.nand2.input_load()