mirror of https://github.com/VLSIDA/OpenRAM.git
Moved majority of code duplicated between delay and functional to simulation
This commit is contained in:
Hunter Nichols
parent
13b1d4613c
commit
d027632bdc
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@ -253,17 +253,6 @@ class delay(simulation):
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self.load = load
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self.load = load
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self.slew = slew
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self.slew = slew
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def add_graph_exclusions(self):
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"""Exclude portions of SRAM from timing graph which are not relevant"""
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# other initializations can only be done during analysis when a bit has been selected
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# for testing.
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self.sram.bank.graph_exclude_precharge()
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self.sram.graph_exclude_addr_dff()
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self.sram.graph_exclude_data_dff()
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self.sram.graph_exclude_ctrl_dffs()
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self.sram.bank.bitcell_array.graph_exclude_replica_col_bits()
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def create_graph(self):
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def create_graph(self):
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"""Creates timing graph to generate the timing paths for the SRAM output."""
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"""Creates timing graph to generate the timing paths for the SRAM output."""
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@ -275,90 +264,6 @@ class delay(simulation):
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self.sram_spc_name = "X{}".format(self.sram.name)
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self.sram_spc_name = "X{}".format(self.sram.name)
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self.sram.build_graph(self.graph,self.sram_spc_name,self.pins)
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self.sram.build_graph(self.graph,self.sram_spc_name,self.pins)
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def set_internal_spice_names(self):
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"""Sets important names for characterization such as Sense amp enable and internal bit nets."""
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port = self.read_ports[0]
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if not OPTS.use_pex:
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self.graph.get_all_paths('{}{}'.format("clk", port),
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'{}{}_{}'.format(self.dout_name, port, self.probe_data))
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sen_with_port = self.get_sen_name(self.graph.all_paths)
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if sen_with_port.endswith(str(port)):
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self.sen_name = sen_with_port[:-len(str(port))]
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else:
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self.sen_name = sen_with_port
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debug.warning("Error occurred while determining SEN name. Can cause faults in simulation.")
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debug.info(2,"s_en name = {}".format(self.sen_name))
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bl_name_port, br_name_port = self.get_bl_name(self.graph.all_paths, port)
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port_pos = -1-len(str(self.probe_data))-len(str(port))
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if bl_name_port.endswith(str(port)+"_"+str(self.probe_data)):
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self.bl_name = bl_name_port[:port_pos] +"{}"+ bl_name_port[port_pos+len(str(port)):]
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elif not bl_name_port[port_pos].isdigit(): # single port SRAM case, bl will not be numbered eg bl_0
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self.bl_name = bl_name_port
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else:
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self.bl_name = bl_name_port
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debug.warning("Error occurred while determining bitline names. Can cause faults in simulation.")
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if br_name_port.endswith(str(port)+"_"+str(self.probe_data)):
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self.br_name = br_name_port[:port_pos] +"{}"+ br_name_port[port_pos+len(str(port)):]
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elif not br_name_port[port_pos].isdigit(): # single port SRAM case, bl will not be numbered eg bl_0
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self.br_name = br_name_port
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else:
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self.br_name = br_name_port
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debug.warning("Error occurred while determining bitline names. Can cause faults in simulation.")
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debug.info(2,"bl name={}, br name={}".format(self.bl_name,self.br_name))
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else:
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self.graph.get_all_paths('{}{}'.format("clk", port),
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'{}{}_{}'.format(self.dout_name, port, self.probe_data))
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self.sen_name = self.get_sen_name(self.graph.all_paths)
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debug.info(2,"s_en name = {}".format(self.sen_name))
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self.bl_name = "bl{0}_{1}".format(port, OPTS.word_size-1)
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self.br_name = "br{0}_{1}".format(port, OPTS.word_size-1)
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debug.info(2,"bl name={}, br name={}".format(self.bl_name,self.br_name))
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def get_sen_name(self, paths, assumed_port=None):
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"""
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Gets the signal name associated with the sense amp enable from input paths.
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Only expects a single path to contain the sen signal name.
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"""
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sa_mods = factory.get_mods(OPTS.sense_amp)
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# Any sense amp instantiated should be identical, any change to that
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# will require some identification to determine the mod desired.
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debug.check(len(sa_mods) == 1, "Only expected one type of Sense Amp. Cannot perform s_en checks.")
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enable_name = sa_mods[0].get_enable_name()
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sen_name = self.get_alias_in_path(paths, enable_name, sa_mods[0])
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if OPTS.use_pex:
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sen_name = sen_name.split('.')[-1]
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return sen_name
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def get_bl_name(self, paths, port):
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"""Gets the signal name associated with the bitlines in the bank."""
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cell_mod = factory.create(module_type=OPTS.bitcell)
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cell_bl = cell_mod.get_bl_name(port)
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cell_br = cell_mod.get_br_name(port)
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bl_found = False
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# Only a single path should contain a single s_en name. Anything else is an error.
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bl_names = []
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exclude_set = self.get_bl_name_search_exclusions()
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for int_net in [cell_bl, cell_br]:
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bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set))
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if OPTS.use_pex:
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for i in range(len(bl_names)):
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bl_names[i] = bl_names[i].split('.')[-1]
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return bl_names[0], bl_names[1]
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def get_bl_name_search_exclusions(self):
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def get_bl_name_search_exclusions(self):
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"""Gets the mods as a set which should be excluded while searching for name."""
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"""Gets the mods as a set which should be excluded while searching for name."""
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@ -420,18 +420,6 @@ class functional(simulation):
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self.stim.write_control(self.cycle_times[-1] + self.period)
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self.stim.write_control(self.cycle_times[-1] + self.period)
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self.sf.close()
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self.sf.close()
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# FIXME: refactor to share with delay.py
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def add_graph_exclusions(self):
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"""Exclude portions of SRAM from timing graph which are not relevant"""
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# other initializations can only be done during analysis when a bit has been selected
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# for testing.
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self.sram.bank.graph_exclude_precharge()
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self.sram.graph_exclude_addr_dff()
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self.sram.graph_exclude_data_dff()
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self.sram.graph_exclude_ctrl_dffs()
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self.sram.bank.bitcell_array.graph_exclude_replica_col_bits()
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# FIXME: refactor to share with delay.py
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# FIXME: refactor to share with delay.py
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def create_graph(self):
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def create_graph(self):
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"""Creates timing graph to generate the timing paths for the SRAM output."""
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"""Creates timing graph to generate the timing paths for the SRAM output."""
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@ -445,24 +433,6 @@ class functional(simulation):
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self.sram_spc_name = "X{}".format(self.sram.name)
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self.sram_spc_name = "X{}".format(self.sram.name)
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self.sram.build_graph(self.graph, self.sram_spc_name, self.pins)
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self.sram.build_graph(self.graph, self.sram_spc_name, self.pins)
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# FIXME: refactor to share with delay.py
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def set_internal_spice_names(self):
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"""Sets important names for characterization such as Sense amp enable and internal bit nets."""
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# For now, only testing these using first read port.
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port = self.read_ports[0]
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self.graph.get_all_paths('{}{}'.format("clk", port),
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'{}{}_{}'.format(self.dout_name, port, 0).lower())
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self.sen_name = self.get_sen_name(self.graph.all_paths)
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debug.info(2, "s_en name = {}".format(self.sen_name))
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self.bl_name, self.br_name = self.get_bl_name(self.graph.all_paths, port)
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debug.info(2, "bl name={}, br name={}".format(self.bl_name, self.br_name))
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self.q_name, self.qbar_name = self.get_bit_name()
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debug.info(2, "q name={}\nqbar name={}".format(self.q_name, self.qbar_name))
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def get_bit_name(self):
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def get_bit_name(self):
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""" Get a bit cell name """
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""" Get a bit cell name """
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(cell_name, cell_inst) = self.sram.get_cell_name(self.sram.name, 0, 0)
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(cell_name, cell_inst) = self.sram.get_cell_name(self.sram.name, 0, 0)
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@ -474,37 +444,6 @@ class functional(simulation):
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return (q_name, qbar_name)
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return (q_name, qbar_name)
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# FIXME: refactor to share with delay.py
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def get_sen_name(self, paths):
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"""
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Gets the signal name associated with the sense amp enable from input paths.
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Only expects a single path to contain the sen signal name.
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"""
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sa_mods = factory.get_mods(OPTS.sense_amp)
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# Any sense amp instantiated should be identical, any change to that
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# will require some identification to determine the mod desired.
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debug.check(len(sa_mods) == 1, "Only expected one type of Sense Amp. Cannot perform s_en checks.")
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enable_name = sa_mods[0].get_enable_name()
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sen_name = self.get_alias_in_path(paths, enable_name, sa_mods[0])
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return sen_name
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# FIXME: refactor to share with delay.py
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def get_bl_name(self, paths, port):
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"""Gets the signal name associated with the bitlines in the bank."""
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cell_mod = factory.create(module_type=OPTS.bitcell)
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cell_bl = cell_mod.get_bl_name(port)
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cell_br = cell_mod.get_br_name(port)
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# Only a single path should contain a single s_en name. Anything else is an error.
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bl_names = []
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exclude_set = self.get_bl_name_search_exclusions()
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for int_net in [cell_bl, cell_br]:
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bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set))
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return bl_names[0], bl_names[1]
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def get_bl_name_search_exclusions(self):
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def get_bl_name_search_exclusions(self):
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"""Gets the mods as a set which should be excluded while searching for name."""
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"""Gets the mods as a set which should be excluded while searching for name."""
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@ -408,3 +408,96 @@ class simulation():
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pin_names.append("{0}".format("gnd"))
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pin_names.append("{0}".format("gnd"))
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return pin_names
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return pin_names
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def add_graph_exclusions(self):
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"""Exclude portions of SRAM from timing graph which are not relevant"""
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# other initializations can only be done during analysis when a bit has been selected
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# for testing.
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self.sram.bank.graph_exclude_precharge()
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self.sram.graph_exclude_addr_dff()
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self.sram.graph_exclude_data_dff()
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self.sram.graph_exclude_ctrl_dffs()
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self.sram.bank.bitcell_array.graph_exclude_replica_col_bits()
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def set_internal_spice_names(self):
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"""Sets important names for characterization such as Sense amp enable and internal bit nets."""
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port = self.read_ports[0]
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if not OPTS.use_pex:
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self.graph.get_all_paths('{}{}'.format("clk", port),
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'{}{}_{}'.format(self.dout_name, port, self.probe_data))
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sen_with_port = self.get_sen_name(self.graph.all_paths)
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if sen_with_port.endswith(str(port)):
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self.sen_name = sen_with_port[:-len(str(port))]
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else:
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self.sen_name = sen_with_port
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debug.warning("Error occurred while determining SEN name. Can cause faults in simulation.")
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debug.info(2,"s_en name = {}".format(self.sen_name))
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bl_name_port, br_name_port = self.get_bl_name(self.graph.all_paths, port)
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port_pos = -1-len(str(self.probe_data))-len(str(port))
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if bl_name_port.endswith(str(port)+"_"+str(self.probe_data)):
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self.bl_name = bl_name_port[:port_pos] +"{}"+ bl_name_port[port_pos+len(str(port)):]
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elif not bl_name_port[port_pos].isdigit(): # single port SRAM case, bl will not be numbered eg bl_0
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self.bl_name = bl_name_port
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else:
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self.bl_name = bl_name_port
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debug.warning("Error occurred while determining bitline names. Can cause faults in simulation.")
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if br_name_port.endswith(str(port)+"_"+str(self.probe_data)):
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self.br_name = br_name_port[:port_pos] +"{}"+ br_name_port[port_pos+len(str(port)):]
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elif not br_name_port[port_pos].isdigit(): # single port SRAM case, bl will not be numbered eg bl_0
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self.br_name = br_name_port
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else:
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self.br_name = br_name_port
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debug.warning("Error occurred while determining bitline names. Can cause faults in simulation.")
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debug.info(2,"bl name={}, br name={}".format(self.bl_name,self.br_name))
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else:
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self.graph.get_all_paths('{}{}'.format("clk", port),
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'{}{}_{}'.format(self.dout_name, port, self.probe_data))
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self.sen_name = self.get_sen_name(self.graph.all_paths)
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debug.info(2,"s_en name = {}".format(self.sen_name))
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self.bl_name = "bl{0}_{1}".format(port, OPTS.word_size-1)
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self.br_name = "br{0}_{1}".format(port, OPTS.word_size-1)
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debug.info(2,"bl name={}, br name={}".format(self.bl_name,self.br_name))
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def get_sen_name(self, paths, assumed_port=None):
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"""
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Gets the signal name associated with the sense amp enable from input paths.
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Only expects a single path to contain the sen signal name.
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"""
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sa_mods = factory.get_mods(OPTS.sense_amp)
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# Any sense amp instantiated should be identical, any change to that
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# will require some identification to determine the mod desired.
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debug.check(len(sa_mods) == 1, "Only expected one type of Sense Amp. Cannot perform s_en checks.")
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enable_name = sa_mods[0].get_enable_name()
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sen_name = self.get_alias_in_path(paths, enable_name, sa_mods[0])
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if OPTS.use_pex:
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sen_name = sen_name.split('.')[-1]
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return sen_name
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def get_bl_name(self, paths, port):
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"""Gets the signal name associated with the bitlines in the bank."""
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cell_mod = factory.create(module_type=OPTS.bitcell)
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cell_bl = cell_mod.get_bl_name(port)
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cell_br = cell_mod.get_br_name(port)
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bl_found = False
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# Only a single path should contain a single s_en name. Anything else is an error.
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bl_names = []
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exclude_set = self.get_bl_name_search_exclusions()
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for int_net in [cell_bl, cell_br]:
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bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set))
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if OPTS.use_pex:
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for i in range(len(bl_names)):
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bl_names[i] = bl_names[i].split('.')[-1]
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return bl_names[0], bl_names[1]
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