mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-03 07:13:29 +02:00
Development version of new pin data structure. Tests pass LVS/DRC except for bank level.
This commit is contained in:
Matt Guthaus
@@ -18,6 +18,7 @@ class contact_test(unittest.TestCase):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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OPTS.check_lvsdrc = False
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import contact
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@@ -27,30 +28,22 @@ class contact_test(unittest.TestCase):
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# Check single 1 x 1 contact"
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debug.info(2, "1 x 1 {} test".format(stack_name))
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OPTS.check_lvsdrc = False
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c = contact.contact(layer_stack, (1, 1))
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OPTS.check_lvsdrc = True
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self.local_check(c)
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# check vertical array with one in the middle and two ends
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debug.info(2, "1 x 3 {} test".format(stack_name))
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OPTS.check_lvsdrc = False
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c = contact.contact(layer_stack, (1, 3))
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OPTS.check_lvsdrc = True
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self.local_check(c)
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# check horizontal array with one in the middle and two ends
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debug.info(2, "3 x 1 {} test".format(stack_name))
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OPTS.check_lvsdrc = False
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c = contact.contact(layer_stack, (3, 1))
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OPTS.check_lvsdrc = True
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self.local_check(c)
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# check 3x3 array for all possible neighbors
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debug.info(2, "3 x 3 {} test".format(stack_name))
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OPTS.check_lvsdrc = False
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c = contact.contact(layer_stack, (3, 3))
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OPTS.check_lvsdrc = True
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self.local_check(c)
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OPTS.check_lvsdrc = True
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@@ -18,6 +18,7 @@ class path_test(unittest.TestCase):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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OPTS.check_lvsdrc = False
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import path
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import tech
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@@ -32,11 +33,9 @@ class path_test(unittest.TestCase):
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[4 * min_space, 3 * min_space ],
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[0, 3 * min_space ],
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[0, 6 * min_space ]]
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OPTS.check_lvsdrc = False
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w = design.design("path_test0")
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path.path(w,layer_stack, position_list)
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self.local_check(w)
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OPTS.check_lvsdrc = True
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min_space = 2 * tech.drc["minwidth_metal1"]
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@@ -51,11 +50,9 @@ class path_test(unittest.TestCase):
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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position_list = [[x+min_space, y+min_space] for x,y in old_position_list]
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OPTS.check_lvsdrc = False
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w = design.design("path_test1")
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path.path(w,layer_stack, position_list)
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self.local_check(w)
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OPTS.check_lvsdrc = True
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min_space = 2 * tech.drc["minwidth_metal2"]
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layer_stack = ("metal2")
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@@ -69,11 +66,9 @@ class path_test(unittest.TestCase):
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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position_list = [[x-min_space, y-min_space] for x,y in old_position_list]
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OPTS.check_lvsdrc = False
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w = design.design("path_test2")
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path.path(w, layer_stack, position_list)
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self.local_check(w)
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OPTS.check_lvsdrc = True
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min_space = 2 * tech.drc["minwidth_metal3"]
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layer_stack = ("metal3")
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@@ -88,11 +83,8 @@ class path_test(unittest.TestCase):
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[-1 * min_space, 0]]
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# run on the reverse list
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position_list.reverse()
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OPTS.check_lvsdrc = False
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w = design.design("path_test3")
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path.path(w, layer_stack, position_list)
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OPTS.check_lvsdrc = True
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self.local_check(w)
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# return it back to it's normal state
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@@ -28,10 +28,9 @@ class ptx_test(unittest.TestCase):
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fet = ptx.ptx(width=tech.drc["minwidth_tx"],
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mults=1,
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tx_type="nmos")
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# return it back to it's normal state
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OPTS.check_lvsdrc = True
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self.local_check(fet)
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OPTS.check_lvsdrc = True
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globals.end_openram()
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@@ -28,10 +28,9 @@ class ptx_test(unittest.TestCase):
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fet = ptx.ptx(width=tech.drc["minwidth_tx"],
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mults=1,
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tx_type="pmos")
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# return it back to it's normal state
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OPTS.check_lvsdrc = True
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self.local_check(fet)
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OPTS.check_lvsdrc = True
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globals.end_openram()
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@@ -28,10 +28,9 @@ class ptx_test(unittest.TestCase):
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fet = ptx.ptx(width=tech.drc["minwidth_tx"],
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mults=3,
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tx_type="nmos")
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# return it back to it's normal state
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OPTS.check_lvsdrc = True
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self.local_check(fet)
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OPTS.check_lvsdrc = True
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globals.end_openram()
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def add_mods(self, fet):
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@@ -28,10 +28,9 @@ class ptx_test(unittest.TestCase):
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fet = ptx.ptx(width=tech.drc["minwidth_tx"],
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mults=3,
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tx_type="pmos")
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# return it back to it's normal state
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OPTS.check_lvsdrc = True
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self.local_check(fet)
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OPTS.check_lvsdrc = True
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globals.end_openram()
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def add_mods(self, fet):
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@@ -18,6 +18,7 @@ class wire_test(unittest.TestCase):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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OPTS.check_lvsdrc = False
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import wire
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import tech
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@@ -36,10 +37,8 @@ class wire_test(unittest.TestCase):
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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position_list = [[x-min_space, y-min_space] for x,y in old_position_list]
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OPTS.check_lvsdrc = False
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w = design.design("wire_test1")
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wire.wire(w, layer_stack, position_list)
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OPTS.check_lvsdrc = True
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self.local_check(w)
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min_space = 2 * (tech.drc["minwidth_poly"] +
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@@ -55,10 +54,8 @@ class wire_test(unittest.TestCase):
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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position_list = [[x+min_space, y+min_space] for x,y in old_position_list]
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OPTS.check_lvsdrc = False
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w = design.design("wire_test2")
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wire.wire(w, layer_stack, position_list)
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OPTS.check_lvsdrc = True
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self.local_check(w)
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min_space = 2 * (tech.drc["minwidth_metal2"] +
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@@ -73,10 +70,8 @@ class wire_test(unittest.TestCase):
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[7 * min_space, 4 * min_space],
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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OPTS.check_lvsdrc = False
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w = design.design("wire_test3")
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wire.wire(w, layer_stack, position_list)
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OPTS.check_lvsdrc = True
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self.local_check(w)
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@@ -92,10 +87,8 @@ class wire_test(unittest.TestCase):
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[7 * min_space, 4 * min_space],
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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OPTS.check_lvsdrc = False
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w = design.design("wire_test4")
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wire.wire(w, layer_stack, position_list)
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OPTS.check_lvsdrc = True
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self.local_check(w)
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min_space = 2 * (tech.drc["minwidth_metal2"] +
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@@ -111,10 +104,8 @@ class wire_test(unittest.TestCase):
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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position_list.reverse()
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OPTS.check_lvsdrc = False
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w = design.design("wire_test5")
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wire.wire(w, layer_stack, position_list)
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OPTS.check_lvsdrc = True
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self.local_check(w)
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min_space = 2 * (tech.drc["minwidth_metal2"] +
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@@ -130,10 +121,8 @@ class wire_test(unittest.TestCase):
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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position_list.reverse()
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OPTS.check_lvsdrc = False
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w = design.design("wire_test6")
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wire.wire(w, layer_stack, position_list)
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OPTS.check_lvsdrc = True
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self.local_check(w)
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# return it back to it's normal state
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@@ -31,8 +31,9 @@ class nand_2_test(unittest.TestCase):
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debug.info(2, "Checking 2-input nand gate")
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tx = nand_2.nand_2(nmos_width=2 * tech.drc["minwidth_tx"])
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OPTS.check_lvsdrc = True
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self.local_check(tx)
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OPTS.check_lvsdrc = True
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globals.end_openram()
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@@ -28,9 +28,9 @@ class nand_3_test(unittest.TestCase):
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debug.info(2, "Checking 3-input nand gate")
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tx = nand_3.nand_3(nmos_width=3 * tech.drc["minwidth_tx"])
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self.local_check(tx)
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OPTS.check_lvsdrc = True
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self.local_check(tx)
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globals.end_openram()
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def local_check(self, tx):
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@@ -30,8 +30,9 @@ class nor_2_test(unittest.TestCase):
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debug.info(2, "Checking 2-input nor gate")
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tx = nor_2.nor_2(nmos_width=2 * tech.drc["minwidth_tx"])
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OPTS.check_lvsdrc = True
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self.local_check(tx)
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OPTS.check_lvsdrc = True
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globals.end_openram()
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def local_check(self, tx):
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@@ -20,28 +20,24 @@ class pinv_test(unittest.TestCase):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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OPTS.check_lvsdrc = False
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import pinv
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import tech
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# debug.info(2, "Checking min size inverter")
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# OPTS.check_lvsdrc = False
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# tx = pinv.pinv(nmos_width=tech.drc["minwidth_tx"], beta=tech.parameter["pinv_beta"])
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# OPTS.check_lvsdrc = True
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# self.local_check(tx)
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# debug.info(2, "Checking 2x min size inverter")
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# OPTS.check_lvsdrc = False
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# tx = pinv.pinv(nmos_width=2 * tech.drc["minwidth_tx"], beta=tech.parameter["pinv_beta"])
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# OPTS.check_lvsdrc = True
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# self.local_check(tx)
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debug.info(2, "Checking 5x min size inverter")
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OPTS.check_lvsdrc = False
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tx = pinv.pinv(nmos_width=5 * tech.drc["minwidth_tx"], beta=tech.parameter["pinv_beta"])
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OPTS.check_lvsdrc = True
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debug.info(2, "Checking min size inverter")
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tx = pinv.pinv(nmos_width=tech.drc["minwidth_tx"], beta=tech.parameter["pinv_beta"])
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self.local_check(tx)
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debug.info(2, "Checking 2x min size inverter")
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tx = pinv.pinv(nmos_width=2 * tech.drc["minwidth_tx"], beta=tech.parameter["pinv_beta"])
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self.local_check(tx)
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debug.info(2, "Checking 5x min size inverter")
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tx = pinv.pinv(nmos_width=5 * tech.drc["minwidth_tx"], beta=tech.parameter["pinv_beta"])
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self.local_check(tx)
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OPTS.check_lvsdrc = True
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globals.end_openram()
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def local_check(self, tx):
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@@ -57,6 +53,10 @@ class pinv_test(unittest.TestCase):
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os.remove(tempspice)
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os.remove(tempgds)
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# reset the static duplicate name checker for unit tests
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import design
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design.design.name_map=[]
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@@ -0,0 +1,52 @@
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#!/usr/bin/env python2.7
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"""
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Run a regresion test on a precharge cell
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"""
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import unittest
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from testutils import header
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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import debug
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import calibre
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import sys
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OPTS = globals.OPTS
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class precharge_test(unittest.TestCase):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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# we will manually run lvs/drc
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OPTS.check_lvsdrc = False
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import precharge
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import tech
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debug.info(2, "Checking precharge")
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tx = precharge.precharge(name="precharge_driver", ptx_width=tech.drc["minwidth_tx"])
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self.local_check(tx)
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OPTS.check_lvsdrc = True
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globals.end_openram()
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def local_check(self, tx):
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tempspice = OPTS.openram_temp + "temp.sp"
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tempgds = OPTS.openram_temp + "temp.gds"
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tx.sp_write(tempspice)
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tx.gds_write(tempgds)
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self.assertFalse(calibre.run_drc(tx.name, tempgds))
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self.assertFalse(calibre.run_lvs(tx.name, tempgds, tempspice))
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os.remove(tempspice)
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os.remove(tempgds)
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# instantiate a copy of the class to actually run the test
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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header(__file__, OPTS.tech_name)
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unittest.main()
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@@ -28,12 +28,12 @@ class wordline_driver_test(unittest.TestCase):
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import tech
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debug.info(2, "Checking driver")
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tx = wordline_driver.wordline_driver(name="Wordline_driver", rows=8)
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tx = wordline_driver.wordline_driver(rows=8)
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self.local_check(tx)
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OPTS.check_lvsdrc = True
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self.local_check(tx)
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globals.end_openram()
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def local_check(self, tx):
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tempspice = OPTS.openram_temp + "temp.sp"
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tempgds = OPTS.openram_temp + "temp.gds"
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@@ -25,12 +25,11 @@ class array_test(unittest.TestCase):
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import bitcell_array
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debug.info(2, "Testing 3x3 array for 6t_cell")
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a = bitcell_array.bitcell_array(name="bitcell_array", cols=3, rows=3)
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debug.info(2, "Testing 4x4 array for 6t_cell")
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a = bitcell_array.bitcell_array(name="bitcell_array", cols=4, rows=4)
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self.local_check(a)
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OPTS.check_lvsdrc = True
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self.local_check(a)
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globals.end_openram()
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def local_check(self, a):
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@@ -18,50 +18,32 @@ class hierarchical_decoder_test(unittest.TestCase):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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OPTS.check_lvsdrc = False
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import hierarchical_decoder
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import tech
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debug.info(1, "Testing 4 row sample for hierarchical_decoder")
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OPTS.check_lvsdrc = False
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a = hierarchical_decoder.hierarchical_decoder(nand2_nmos_width=2 * tech.drc["minwidth_tx"],
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nand3_nmos_width=3 * tech.drc["minwidth_tx"],
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rows=4)
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OPTS.check_lvsdrc = True
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a = hierarchical_decoder.hierarchical_decoder(rows=4)
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self.local_check(a)
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debug.info(1, "Testing 8 row sample for hierarchical_decoder")
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OPTS.check_lvsdrc = False
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a = hierarchical_decoder.hierarchical_decoder(nand2_nmos_width=2 * tech.drc["minwidth_tx"],
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nand3_nmos_width=3 * tech.drc["minwidth_tx"],
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rows=8)
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OPTS.check_lvsdrc = True
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a = hierarchical_decoder.hierarchical_decoder(rows=8)
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self.local_check(a)
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debug.info(1, "Testing 32 row sample for hierarchical_decoder")
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OPTS.check_lvsdrc = False
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a = hierarchical_decoder.hierarchical_decoder(nand2_nmos_width=2 * tech.drc["minwidth_tx"],
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nand3_nmos_width=3 * tech.drc["minwidth_tx"],
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rows=32)
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OPTS.check_lvsdrc = True
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a = hierarchical_decoder.hierarchical_decoder(rows=32)
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self.local_check(a)
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debug.info(1, "Testing 128 row sample for hierarchical_decoder")
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OPTS.check_lvsdrc = False
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a = hierarchical_decoder.hierarchical_decoder(nand2_nmos_width=2 * tech.drc["minwidth_tx"],
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nand3_nmos_width=3 * tech.drc["minwidth_tx"],
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rows=128)
|
||||
OPTS.check_lvsdrc = True
|
||||
a = hierarchical_decoder.hierarchical_decoder(rows=128)
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(1, "Testing 512 row sample for hierarchical_decoder")
|
||||
OPTS.check_lvsdrc = False
|
||||
a = hierarchical_decoder.hierarchical_decoder(nand2_nmos_width=2 * tech.drc["minwidth_tx"],
|
||||
nand3_nmos_width=3 * tech.drc["minwidth_tx"],
|
||||
rows=512)
|
||||
OPTS.check_lvsdrc = True
|
||||
a = hierarchical_decoder.hierarchical_decoder(rows=512)
|
||||
self.local_check(a)
|
||||
|
||||
OPTS.check_lvsdrc = True
|
||||
globals.end_openram()
|
||||
|
||||
def local_check(self, a):
|
||||
@@ -77,6 +59,11 @@ class hierarchical_decoder_test(unittest.TestCase):
|
||||
os.remove(tempspice)
|
||||
os.remove(tempgds)
|
||||
|
||||
# reset the static duplicate name checker for unit tests
|
||||
import design
|
||||
design.design.name_map=[]
|
||||
|
||||
|
||||
# instantiate a copdsay of the class to actually run the test
|
||||
if __name__ == "__main__":
|
||||
(OPTS, args) = globals.parse_args()
|
||||
|
||||
@@ -24,12 +24,11 @@ class hierarchical_predecode2x4_test(unittest.TestCase):
|
||||
import hierarchical_predecode2x4 as pre
|
||||
import tech
|
||||
|
||||
debug.info(1, "Testing sample for hierarchy_decoder")
|
||||
a = pre.hierarchical_predecode2x4(nmos_width=2 * tech.drc["minwidth_tx"],
|
||||
cellname="test_pre2x4")
|
||||
OPTS.check_lvsdrc = True
|
||||
debug.info(1, "Testing sample for hierarchy_predecode2x4")
|
||||
a = pre.hierarchical_predecode2x4()
|
||||
self.local_check(a)
|
||||
|
||||
OPTS.check_lvsdrc = True
|
||||
globals.end_openram()
|
||||
|
||||
def local_check(self, a):
|
||||
|
||||
@@ -24,12 +24,11 @@ class hierarchical_predecode3x8_test(unittest.TestCase):
|
||||
import hierarchical_predecode3x8 as pre
|
||||
import tech
|
||||
|
||||
debug.info(1, "Testing sample for hierarchy_decoder")
|
||||
a = pre.hierarchical_predecode3x8(nmos_width=3 * tech.drc["minwidth_tx"],
|
||||
cellname="test_pre3x8")
|
||||
OPTS.check_lvsdrc = True
|
||||
debug.info(1, "Testing sample for hierarchy_predecode3x8")
|
||||
a = pre.hierarchical_predecode3x8()
|
||||
self.local_check(a)
|
||||
|
||||
OPTS.check_lvsdrc = True
|
||||
globals.end_openram()
|
||||
|
||||
def local_check(self, a):
|
||||
|
||||
+16
-6
@@ -22,12 +22,20 @@ class single_level_column_mux_test(unittest.TestCase):
|
||||
OPTS.check_lvsdrc = False
|
||||
|
||||
import single_level_column_mux_array
|
||||
|
||||
debug.info(1, "Testing sample for columnmux_array")
|
||||
a = single_level_column_mux_array.single_level_column_mux_array(
|
||||
rows=32, columns=32, word_size=16)
|
||||
OPTS.check_lvsdrc = True
|
||||
|
||||
debug.info(1, "Testing sample for 2-way column_mux_array")
|
||||
a = single_level_column_mux_array.single_level_column_mux_array(columns=16, word_size=8)
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(1, "Testing sample for 4-way column_mux_array")
|
||||
a = single_level_column_mux_array.single_level_column_mux_array(columns=16, word_size=4)
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(1, "Testing sample for 8-way column_mux_array")
|
||||
a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4)
|
||||
self.local_check(a)
|
||||
|
||||
OPTS.check_lvsdrc = True
|
||||
globals.end_openram()
|
||||
|
||||
def local_check(self, a):
|
||||
@@ -43,7 +51,9 @@ class single_level_column_mux_test(unittest.TestCase):
|
||||
os.remove(tempspice)
|
||||
os.remove(tempgds)
|
||||
|
||||
OPTS.check_lvsdrc = True
|
||||
# reset the static duplicate name checker for unit tests
|
||||
import design
|
||||
design.design.name_map=[]
|
||||
|
||||
# instantiate a copdsay of the class to actually run the test
|
||||
if __name__ == "__main__":
|
||||
@@ -20,17 +20,16 @@ class precharge_test(unittest.TestCase):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
|
||||
OPTS.check_lvsdrc = False
|
||||
|
||||
import precharge_array
|
||||
import tech
|
||||
|
||||
debug.info(2, "Checking 3 column precharge")
|
||||
OPTS.check_lvsdrc = False
|
||||
pc = precharge_array.precharge_array(
|
||||
name="precharge_array", columns=3, ptx_width=tech.drc["minwidth_tx"], beta=2)
|
||||
OPTS.check_lvsdrc = True
|
||||
pc = precharge_array.precharge_array(columns=3, ptx_width=tech.drc["minwidth_tx"], beta=2)
|
||||
self.local_check(pc)
|
||||
|
||||
OPTS.check_lvsdrc = True
|
||||
globals.end_openram()
|
||||
|
||||
def local_check(self, pc):
|
||||
|
||||
@@ -20,16 +20,20 @@ class sense_amp_test(unittest.TestCase):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
|
||||
OPTS.check_lvsdrc = False
|
||||
|
||||
import sense_amp_array
|
||||
|
||||
|
||||
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2")
|
||||
OPTS.check_lvsdrc = False
|
||||
a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=2)
|
||||
OPTS.check_lvsdrc = True
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4")
|
||||
a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=4)
|
||||
self.local_check(a)
|
||||
|
||||
OPTS.check_lvsdrc = True
|
||||
globals.end_openram()
|
||||
|
||||
def local_check(self, a):
|
||||
@@ -45,6 +49,11 @@ class sense_amp_test(unittest.TestCase):
|
||||
os.remove(tempspice)
|
||||
os.remove(tempgds)
|
||||
|
||||
# reset the static duplicate name checker for unit tests
|
||||
import design
|
||||
design.design.name_map=[]
|
||||
|
||||
|
||||
# instantiate a copy of the class to actually run the test
|
||||
if __name__ == "__main__":
|
||||
(OPTS, args) = globals.parse_args()
|
||||
|
||||
@@ -20,15 +20,19 @@ class write_driver_test(unittest.TestCase):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
|
||||
OPTS.check_lvsdrc = False
|
||||
|
||||
import write_driver_array
|
||||
|
||||
debug.info(2, "Testing write_driver_array for columns=128, word_size=128")
|
||||
OPTS.check_lvsdrc = False
|
||||
a = write_driver_array.write_driver_array(columns=16, word_size=16)
|
||||
OPTS.check_lvsdrc = True
|
||||
debug.info(2, "Testing write_driver_array for columns=8, word_size=8")
|
||||
a = write_driver_array.write_driver_array(columns=8, word_size=8)
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(2, "Testing write_driver_array for columns=16, word_size=8")
|
||||
a = write_driver_array.write_driver_array(columns=16, word_size=8)
|
||||
self.local_check(a)
|
||||
|
||||
OPTS.check_lvsdrc = True
|
||||
globals.end_openram()
|
||||
|
||||
def local_check(self, a):
|
||||
@@ -44,6 +48,11 @@ class write_driver_test(unittest.TestCase):
|
||||
os.remove(tempspice)
|
||||
os.remove(tempgds)
|
||||
|
||||
# reset the static duplicate name checker for unit tests
|
||||
import design
|
||||
design.design.name_map=[]
|
||||
|
||||
|
||||
# instantiate a copy of the class to actually run the test
|
||||
if __name__ == "__main__":
|
||||
(OPTS, args) = globals.parse_args()
|
||||
|
||||
@@ -21,16 +21,19 @@ class dff_array_test(unittest.TestCase):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
|
||||
OPTS.check_lvsdrc = False
|
||||
|
||||
import ms_flop_array
|
||||
|
||||
debug.info(1, "Testing sample for dff_array")
|
||||
OPTS.check_lvsdrc = False
|
||||
a = ms_flop_array.ms_flop_array(
|
||||
name="test1", columns=64, word_size=32)
|
||||
OPTS.check_lvsdrc = True
|
||||
debug.info(2, "Testing ms_flop_array for columns=8, word_size=8")
|
||||
a = ms_flop_array.ms_flop_array(columns=8, word_size=8)
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(2, "Testing ms_flop_array for columns=16, word_size=8")
|
||||
a = ms_flop_array.ms_flop_array(columns=16, word_size=8)
|
||||
self.local_check(a)
|
||||
|
||||
OPTS.check_lvsdrc = True
|
||||
globals.end_openram()
|
||||
|
||||
def local_check(self, a):
|
||||
@@ -46,6 +49,11 @@ class dff_array_test(unittest.TestCase):
|
||||
os.remove(tempspice)
|
||||
os.remove(tempgds)
|
||||
|
||||
# reset the static duplicate name checker for unit tests
|
||||
import design
|
||||
design.design.name_map=[]
|
||||
|
||||
|
||||
|
||||
# instantiate a copdsay of the class to actually run the test
|
||||
if __name__ == "__main__":
|
||||
|
||||
+12
-3
@@ -23,11 +23,15 @@ class tri_gate_array_test(unittest.TestCase):
|
||||
|
||||
import tri_gate_array
|
||||
|
||||
debug.info(1, "Testing sample for tri_gate_array")
|
||||
a = tri_gate_array.tri_gate_array(columns=16, word_size=16)
|
||||
OPTS.check_lvsdrc = True
|
||||
debug.info(1, "Testing tri_gate_array for columns=8, word_size=8")
|
||||
a = tri_gate_array.tri_gate_array(columns=8, word_size=8)
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(1, "Testing tri_gate_array for columns=16, word_size=8")
|
||||
a = tri_gate_array.tri_gate_array(columns=16, word_size=8)
|
||||
self.local_check(a)
|
||||
|
||||
OPTS.check_lvsdrc = True
|
||||
globals.end_openram()
|
||||
|
||||
def local_check(self, a):
|
||||
@@ -43,6 +47,11 @@ class tri_gate_array_test(unittest.TestCase):
|
||||
os.remove(tempspice)
|
||||
os.remove(tempgds)
|
||||
|
||||
# reset the static duplicate name checker for unit tests
|
||||
import design
|
||||
design.design.name_map=[]
|
||||
|
||||
|
||||
# instantiate a copdsay of the class to actually run the test
|
||||
if __name__ == "__main__":
|
||||
(OPTS, args) = globals.parse_args()
|
||||
+2
-2
@@ -27,10 +27,10 @@ class replica_bitline_test(unittest.TestCase):
|
||||
import replica_bitline
|
||||
|
||||
debug.info(2, "Testing RBL")
|
||||
a = replica_bitline.replica_bitline("chain", 13)
|
||||
OPTS.check_lvsdrc = True
|
||||
a = replica_bitline.replica_bitline(13)
|
||||
self.local_check(a)
|
||||
|
||||
OPTS.check_lvsdrc = True
|
||||
globals.end_openram()
|
||||
|
||||
def local_check(self, a):
|
||||
@@ -16,21 +16,20 @@ OPTS = globals.get_opts()
|
||||
#@unittest.skip("SKIPPING 14_delay_chain_test")
|
||||
|
||||
|
||||
class logic_effort_dc_test(unittest.TestCase):
|
||||
class delay_chain_test(unittest.TestCase):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
|
||||
# we will manually run lvs/drc
|
||||
OPTS.check_lvsdrc = False
|
||||
|
||||
import logic_effort_dc
|
||||
import delay_chain
|
||||
|
||||
debug.info(2, "Testing delay_chain")
|
||||
a = logic_effort_dc.logic_effort_dc(
|
||||
"chain", stage_list=[4, 4, 4, 4, 4])
|
||||
OPTS.check_lvsdrc = True
|
||||
a = delay_chain.delay_chain(fanout_list=[4, 4, 4, 4])
|
||||
self.local_check(a)
|
||||
|
||||
OPTS.check_lvsdrc = True
|
||||
globals.end_openram()
|
||||
|
||||
def local_check(self, a):
|
||||
@@ -26,9 +26,9 @@ class control_logic_test(unittest.TestCase):
|
||||
|
||||
debug.info(1, "Testing sample for control_logic")
|
||||
a = control_logic.control_logic(num_rows=128)
|
||||
OPTS.check_lvsdrc = True
|
||||
self.local_check(a)
|
||||
|
||||
OPTS.check_lvsdrc = True
|
||||
globals.end_openram()
|
||||
|
||||
def local_check(self, a):
|
||||
@@ -25,16 +25,23 @@ class bank_test(unittest.TestCase):
|
||||
|
||||
import bank
|
||||
|
||||
# override these from the config file
|
||||
OPTS.word_size=8
|
||||
OPTS.num_words=128
|
||||
OPTS.num_banks=1
|
||||
|
||||
debug.info(1, "Testing sample 8bit, 64word BANK")
|
||||
a = bank.bank(word_size=OPTS.num_words, num_words=OPTS.num_words, words_per_row=2, num_banks=OPTS.num_banks, name="test_sram1")
|
||||
OPTS.check_lvsdrc = True
|
||||
debug.info(1, "No column mux")
|
||||
a = bank.bank(word_size=4, num_words=64, words_per_row=2, num_banks=1, name="test_sram1")
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(1, "Two way column mux")
|
||||
a = bank.bank(word_size=4, num_words=64, words_per_row=2, num_banks=1, name="test_sram2")
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(1, "Four way column mux")
|
||||
a = bank.bank(word_size=4, num_words=64, words_per_row=4, num_banks=1, name="test_sram3")
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(1, "Eight way column mux")
|
||||
a = bank.bank(word_size=2, num_words=64, words_per_row=8, num_banks=1, name="test_sram4")
|
||||
self.local_check(a)
|
||||
|
||||
OPTS.check_lvsdrc = True
|
||||
globals.end_openram()
|
||||
|
||||
def local_check(self, a):
|
||||
|
||||
@@ -27,9 +27,9 @@ class sram_1bank_test(unittest.TestCase):
|
||||
|
||||
debug.info(1, "Testing sample 8bit, 64word SRAM, 1 bank")
|
||||
a = sram.sram(word_size=8, num_words=128, num_banks=1, name="test_sram1")
|
||||
OPTS.check_lvsdrc = True
|
||||
self.local_check(a)
|
||||
|
||||
OPTS.check_lvsdrc = True
|
||||
globals.end_openram()
|
||||
|
||||
def local_check(self, a):
|
||||
|
||||
@@ -27,9 +27,9 @@ class sram_2bank_test(unittest.TestCase):
|
||||
|
||||
debug.info(1, "Testing sample 8bit, 128word SRAM, 2 banks")
|
||||
a = sram.sram(word_size=8, num_words=128, num_banks=2, name="test_sram1")
|
||||
OPTS.check_lvsdrc = True
|
||||
self.local_check(a)
|
||||
|
||||
OPTS.check_lvsdrc = True
|
||||
globals.end_openram()
|
||||
|
||||
def local_check(self, a):
|
||||
|
||||
@@ -27,9 +27,9 @@ class sram_4bank_test(unittest.TestCase):
|
||||
|
||||
debug.info(1, "Testing sample 8bit, 128word SRAM, 4 banks")
|
||||
a = sram.sram(word_size=8, num_words=128, num_banks=4, name="test_sram1")
|
||||
OPTS.check_lvsdrc = True
|
||||
self.local_check(a)
|
||||
|
||||
OPTS.check_lvsdrc = True
|
||||
globals.end_openram()
|
||||
|
||||
def local_check(self, a):
|
||||
|
||||
@@ -22,6 +22,7 @@ write_driver_array = "write_driver_array"
|
||||
tri_gate = "tri_gate"
|
||||
tri_gate_array = "tri_gate_array"
|
||||
wordline_driver = "wordline_driver"
|
||||
replica_bitline = "replica_bitline"
|
||||
replica_bitcell = "replica_bitcell"
|
||||
bitcell = "bitcell"
|
||||
delay_chain = "logic_effort_dc"
|
||||
delay_chain = "delay_chain"
|
||||
|
||||
@@ -22,6 +22,7 @@ write_driver_array = "write_driver_array"
|
||||
tri_gate = "tri_gate"
|
||||
tri_gate_array = "tri_gate_array"
|
||||
wordline_driver = "wordline_driver"
|
||||
replica_bitline = "replica_bitline"
|
||||
replica_bitcell = "replica_bitcell"
|
||||
bitcell = "bitcell"
|
||||
delay_chain = "logic_effort_dc"
|
||||
delay_chain = "delay_chain"
|
||||
|
||||
Reference in New Issue
Block a user