mirror of https://github.com/VLSIDA/OpenRAM.git
Correcting functional inheritance from simulation.
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e258199fa3
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cf4b216888
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@ -19,7 +19,7 @@ class functional(simulation):
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"""
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"""
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def __init__(self, sram, spfile, corner):
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def __init__(self, sram, spfile, corner):
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super().__init__(sram, spfile, corner)
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simulation.__init__(self, sram, spfile, corner)
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self.set_corner(corner)
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self.set_corner(corner)
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self.set_spice_constants()
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self.set_spice_constants()
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@ -64,10 +64,10 @@ class stimuli():
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for readwrite_port in range(readwrite_num):
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for readwrite_port in range(readwrite_num):
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self.sf.write("WEB{0} ".format(readwrite_port))
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self.sf.write("WEB{0} ".format(readwrite_port))
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for port in range(total_port_num):
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#for port in range(total_port_num):
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self.sf.write("CLK{0} ".format(port))
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# self.sf.write("CLK{0} ".format(port))
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#self.sf.write("{0} ".format(tech.spice["clk"]))
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self.sf.write("{0} ".format(tech.spice["clk"]))
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for read_output in read_ports:
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for read_output in read_ports:
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for i in range(dbits):
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for i in range(dbits):
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self.sf.write("DOUT{0}[{1}] ".format(read_output, i))
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self.sf.write("DOUT{0}[{1}] ".format(read_output, i))
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