luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Add wl_en

This commit is contained in:
Matt Guthaus 2018-11-26 18:00:59 -08:00
parent 9e0b31d685
commit cf23eacd0e
4 changed files with 77 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
compiler/modules/bank.py
View File

@ -85,11 +85,12 @@ class bank(design.design):
self.add_pin("bank_sel{}".format(port),"INPUT") self.add_pin("bank_sel{}".format(port),"INPUT")
for port in self.read_ports: for port in self.read_ports:
self.add_pin("s_en{0}".format(port), "INPUT") self.add_pin("s_en{0}".format(port), "INPUT")
for port in self.read_ports:
self.add_pin("p_en{0}".format(port), "INPUT")
for port in self.write_ports: for port in self.write_ports:
self.add_pin("w_en{0}".format(port), "INPUT") self.add_pin("w_en{0}".format(port), "INPUT")
for port in self.all_ports: for port in self.all_ports:
self.add_pin("clk_buf_bar{0}".format(port),"INPUT") self.add_pin("wl_en{0}".format(port), "INPUT")
self.add_pin("clk_buf{0}".format(port),"INPUT")
self.add_pin("vdd","POWER") self.add_pin("vdd","POWER")
self.add_pin("gnd","GROUND") self.add_pin("gnd","GROUND")
@ -355,13 +356,13 @@ class bank(design.design):
self.input_control_signals = [] self.input_control_signals = []
port_num = 0 port_num = 0
for port in range(OPTS.num_rw_ports): for port in range(OPTS.num_rw_ports):
self.input_control_signals.append(["clk_buf{}".format(port_num), "clk_buf_bar{}".format(port_num), "w_en{}".format(port_num), "s_en{}".format(port_num)]) self.input_control_signals.append(["clk_buf{}".format(port_num), "wl_en{}".format(port_num), "w_en{}".format(port_num), "s_en{}".format(port_num), "p_en{}".format(port_num)])
port_num += 1 port_num += 1
for port in range(OPTS.num_w_ports): for port in range(OPTS.num_w_ports):
self.input_control_signals.append(["clk_buf{}".format(port_num), "clk_buf_bar{}".format(port_num), "w_en{}".format(port_num)]) self.input_control_signals.append(["clk_buf{}".format(port_num), "wl_en{}".format(port_num), "w_en{}".format(port_num)])
port_num += 1 port_num += 1
for port in range(OPTS.num_r_ports): for port in range(OPTS.num_r_ports):
self.input_control_signals.append(["clk_buf{}".format(port_num), "clk_buf_bar{}".format(port_num), "s_en{}".format(port_num)]) self.input_control_signals.append(["clk_buf{}".format(port_num), "wl_en{}".format(port_num), "s_en{}".format(port_num), "p_en{}".format(port_num)])
port_num += 1 port_num += 1
# These will be outputs of the gaters if this is multibank, if not, normal signals. # These will be outputs of the gaters if this is multibank, if not, normal signals.
@ -489,7 +490,7 @@ class bank(design.design):
for i in range(self.num_cols): for i in range(self.num_cols):
temp.append(self.bl_names[port]+"_{0}".format(i)) temp.append(self.bl_names[port]+"_{0}".format(i))
temp.append(self.br_names[port]+"_{0}".format(i)) temp.append(self.br_names[port]+"_{0}".format(i))
temp.extend([self.prefix+"clk_buf_bar{0}".format(port), "vdd"]) temp.extend([self.prefix+"p_en{0}".format(port), "vdd"])
self.connect_inst(temp) self.connect_inst(temp)
@ -664,7 +665,7 @@ class bank(design.design):
temp.append("dec_out{0}_{1}".format(port,row)) temp.append("dec_out{0}_{1}".format(port,row))
for row in range(self.num_rows): for row in range(self.num_rows):
temp.append(self.wl_names[port]+"_{0}".format(row)) temp.append(self.wl_names[port]+"_{0}".format(row))
temp.append(self.prefix+"clk_buf{0}".format(port)) temp.append(self.prefix+"wl_en{0}".format(port))
temp.append("vdd") temp.append("vdd")
temp.append("gnd") temp.append("gnd")
self.connect_inst(temp) self.connect_inst(temp)
@ -774,14 +775,14 @@ class bank(design.design):
""" Route the bank select logic. """ """ Route the bank select logic. """
if self.port_id[port] == "rw": if self.port_id[port] == "rw":
bank_sel_signals = ["clk_buf", "clk_buf_bar", "w_en", "s_en", "bank_sel"] bank_sel_signals = ["clk_buf", "w_en", "s_en", "p_en", "bank_sel"]
gated_bank_sel_signals = ["gated_clk_buf", "gated_clk_buf_bar", "gated_w_en", "gated_s_en"] gated_bank_sel_signals = ["gated_clk_buf", "gated_w_en", "gated_s_en", "gated_p_en"]
elif self.port_id[port] == "w": elif self.port_id[port] == "w":
bank_sel_signals = ["clk_buf", "clk_buf_bar", "w_en", "bank_sel"] bank_sel_signals = ["clk_buf", "w_en", "bank_sel"]
gated_bank_sel_signals = ["gated_clk_buf", "gated_clk_buf_bar", "gated_w_en"] gated_bank_sel_signals = ["gated_clk_buf", "gated_w_en"]
else: else:
bank_sel_signals = ["clk_buf", "clk_buf_bar", "s_en", "bank_sel"] bank_sel_signals = ["clk_buf", "s_en", "p_en", "bank_sel"]
gated_bank_sel_signals = ["gated_clk_buf", "gated_clk_buf_bar", "gated_s_en"] gated_bank_sel_signals = ["gated_clk_buf", "gated_s_en", "gated_p_en"]
copy_control_signals = self.input_control_signals[port]+["bank_sel{}".format(port)] copy_control_signals = self.input_control_signals[port]+["bank_sel{}".format(port)]
for signal in range(len(copy_control_signals)): for signal in range(len(copy_control_signals)):
@ -1209,7 +1210,7 @@ class bank(design.design):
connection = [] connection = []
if port in self.read_ports: if port in self.read_ports:
connection.append((self.prefix+"clk_buf_bar{}".format(port), self.precharge_array_inst[port].get_pin("en").lc())) connection.append((self.prefix+"p_en{}".format(port), self.precharge_array_inst[port].get_pin("en").lc()))
if port in self.write_ports: if port in self.write_ports:
connection.append((self.prefix+"w_en{}".format(port), self.write_driver_array_inst[port].get_pin("en").lc())) connection.append((self.prefix+"w_en{}".format(port), self.write_driver_array_inst[port].get_pin("en").lc()))
@ -1225,7 +1226,7 @@ class bank(design.design):
rotate=90) rotate=90)
# clk to wordline_driver # clk to wordline_driver
control_signal = self.prefix+"clk_buf{}".format(port) control_signal = self.prefix+"p_en{}".format(port)
pin_pos = self.wordline_driver_inst[port].get_pin("en").bc() pin_pos = self.wordline_driver_inst[port].get_pin("en").bc()
mid_pos = pin_pos - vector(0,self.m1_pitch) mid_pos = pin_pos - vector(0,self.m1_pitch)
control_x_offset = self.bus_xoffset[port][control_signal].x control_x_offset = self.bus_xoffset[port][control_signal].x

58
compiler/modules/control_logic.py
View File

@ -92,8 +92,8 @@ class control_logic(design.design):
# self.add_mod(self.inv1) # self.add_mod(self.inv1)
# self.inv2 = pinv(size=4, height=dff_height) # self.inv2 = pinv(size=4, height=dff_height)
# self.add_mod(self.inv2) # self.add_mod(self.inv2)
# self.inv8 = pinv(size=16, height=dff_height) self.inv16 = pinv(size=16, height=dff_height)
# self.add_mod(self.inv8) self.add_mod(self.inv16)
if (self.port_type == "rw") or (self.port_type == "r"): if (self.port_type == "rw") or (self.port_type == "r"):
from importlib import reload from importlib import reload
@ -134,9 +134,9 @@ class control_logic(design.design):
# list of output control signals (for making a vertical bus) # list of output control signals (for making a vertical bus)
if self.port_type == "rw": if self.port_type == "rw":
self.internal_bus_list = ["clk_buf", "gated_clk", "we", "we_bar", "cs"] self.internal_bus_list = ["clk_buf", "gated_clk", "we", "we_bar", "pre_p_en", "cs"]
else: else:
self.internal_bus_list = ["clk_buf", "gated_clk", "cs"] self.internal_bus_list = ["clk_buf", "gated_clk", "pre_p_en", "cs"]
# leave space for the bus plus one extra space # leave space for the bus plus one extra space
self.internal_bus_width = (len(self.internal_bus_list)+1)*self.m2_pitch self.internal_bus_width = (len(self.internal_bus_list)+1)*self.m2_pitch
@ -147,6 +147,7 @@ class control_logic(design.design):
self.output_list = ["w_en"] self.output_list = ["w_en"]
else: else:
self.output_list = ["s_en", "w_en", "p_en"] self.output_list = ["s_en", "w_en", "p_en"]
self.output_list.append("wl_en")
self.output_list.append("clk_buf") self.output_list.append("clk_buf")
self.supply_list = ["vdd", "gnd"] self.supply_list = ["vdd", "gnd"]
@ -164,8 +165,9 @@ class control_logic(design.design):
""" Create all the instances """ """ Create all the instances """
self.create_dffs() self.create_dffs()
self.create_clk_rows() self.create_clk_rows()
self.create_wlen_row()
if (self.port_type == "rw") or (self.port_type == "w"): if (self.port_type == "rw") or (self.port_type == "w"):
self.create_we_row() self.create_wen_row()
if (self.port_type == "rw") or (self.port_type == "r"): if (self.port_type == "rw") or (self.port_type == "r"):
self.create_pen_row() self.create_pen_row()
self.create_sen_row() self.create_sen_row()
@ -183,19 +185,23 @@ class control_logic(design.design):
row = 0 row = 0
# Add the logic on the right of the bus # Add the logic on the right of the bus
self.place_clkbuf_row(row=row) self.place_clkbuf_row(row)
row += 1 row += 1
self.place_gated_clk_row(row=row) self.place_gated_clk_row(row)
row += 1
self.place_wlen_row(row)
row += 1 row += 1
if (self.port_type == "rw") or (self.port_type == "w"): if (self.port_type == "rw") or (self.port_type == "w"):
self.place_we_row(row=row) self.place_we_row(row)
height = self.w_en_inst.uy() height = self.w_en_inst.uy()
control_center_y = self.w_en_inst.uy() control_center_y = self.w_en_inst.uy()
row += 1 row += 1
if (self.port_type == "rw") or (self.port_type == "r"): if (self.port_type == "rw") or (self.port_type == "r"):
self.place_pen_row(row=row) self.place_pen_row(row)
self.place_sen_row(row=row+1) row += 1
self.place_rbl(row=row+2) self.place_sen_row(row)
row += 1
self.place_rbl(row)
height = self.rbl_inst.uy() height = self.rbl_inst.uy()
control_center_y = self.rbl_inst.by() control_center_y = self.rbl_inst.by()
@ -214,6 +220,7 @@ class control_logic(design.design):
""" Routing between modules """ """ Routing between modules """
self.route_rails() self.route_rails()
self.route_dffs() self.route_dffs()
self.route_wlen()
if (self.port_type == "rw") or (self.port_type == "w"): if (self.port_type == "rw") or (self.port_type == "w"):
self.route_wen() self.route_wen()
if (self.port_type == "rw") or (self.port_type == "r"): if (self.port_type == "rw") or (self.port_type == "r"):
@ -264,8 +271,24 @@ class control_logic(design.design):
offset = vector(x_off,y_off) offset = vector(x_off,y_off)
self.gated_clk_inst.place(offset) self.gated_clk_inst.place(offset)
self.row_end_inst.append(self.gated_clk_inst) self.row_end_inst.append(self.gated_clk_inst)
def create_wlen_row(self):
# input pre_p_en, output: wl_en
self.p_en_inst=self.add_inst(name="buf_wl_en",
mod=self.inv16)
self.connect_inst(["pre_p_en", "wl_en", "vdd", "gnd"])
def place_wlen_row(self, row):
x_off = self.ctrl_dff_array.width + self.internal_bus_width
(y_off,mirror)=self.get_offset(row)
self.wl_en_offset = vector(x_off, y_off)
self.wl_en_inst.place(offset=self.wl_en_offset,
mirror=mirror)
self.row_end_inst.append(self.wl_en_inst)
def create_pen_row(self): def create_pen_row(self):
# input: gated_clk, we_bar, output: pre_p_en # input: gated_clk, we_bar, output: pre_p_en
self.pre_p_en_inst=self.add_inst(name="and2_pre_p_en", self.pre_p_en_inst=self.add_inst(name="and2_pre_p_en",
@ -287,7 +310,6 @@ class control_logic(design.design):
self.pre_p_en_offset = vector(x_off, y_off) self.pre_p_en_offset = vector(x_off, y_off)
self.pre_p_en_inst.place(offset=self.pre_p_en_offset, self.pre_p_en_inst.place(offset=self.pre_p_en_offset,
mirror=mirror) mirror=mirror)
x_off += self.and2.width
self.row_end_inst.append(self.pre_p_en_inst) self.row_end_inst.append(self.pre_p_en_inst)
@ -359,7 +381,7 @@ class control_logic(design.design):
return (y_off,mirror) return (y_off,mirror)
def create_we_row(self): def create_wen_row(self):
# input: we, gated_clk output: pre_w_en # input: we, gated_clk output: pre_w_en
if self.port_type == "rw": if self.port_type == "rw":
self.pre_w_en_inst = self.add_inst(name="and_pre_w_en", self.pre_w_en_inst = self.add_inst(name="and_pre_w_en",
@ -371,12 +393,12 @@ class control_logic(design.design):
input_name = "gated_clk" input_name = "gated_clk"
# BUFFER FOR W_EN # BUFFER FOR W_EN
self.w_en_inst = self.add_inst(name="w_en_buf", self.w_en_inst = self.add_inst(name="buf_w_en_buf",
mod=self.pbuf8) mod=self.pbuf8)
self.connect_inst([input_name, "w_en", "vdd", "gnd"]) self.connect_inst([input_name, "w_en", "vdd", "gnd"])
def place_we_row(self,row): def place_wen_row(self,row):
x_off = self.ctrl_dff_inst.width + self.internal_bus_width x_off = self.ctrl_dff_inst.width + self.internal_bus_width
(y_off,mirror)=self.get_offset(row) (y_off,mirror)=self.get_offset(row)
@ -461,6 +483,12 @@ class control_logic(design.design):
rotate=90) rotate=90)
def route_wen(self):
wlen_map = zip(["A"], ["pre_p_en"])
self.connect_vertical_bus(wlen_map, self.wl_en_inst, self.rail_offsets)
self.connect_output(self.wl_en_inst, "Z", "wl_en")
def route_wen(self): def route_wen(self):
if self.port_type == "rw": if self.port_type == "rw":

4
compiler/options.py
View File

@ -13,8 +13,8 @@ class options(optparse.Values):
# This is the name of the technology. # This is the name of the technology.
tech_name = "" tech_name = ""
# This is the temp directory where all intermediate results are stored. # This is the temp directory where all intermediate results are stored.
openram_temp = "/tmp/openram_{0}_{1}_temp/".format(getpass.getuser(),os.getpid()) #openram_temp = "/tmp/openram_{0}_{1}_temp/".format(getpass.getuser(),os.getpid())
#openram_temp = "{0}/openram_temp/".format(os.getenv("HOME")) openram_temp = "{0}/openram_temp/".format(os.getenv("HOME"))
# This is the verbosity level to control debug information. 0 is none, 1 # This is the verbosity level to control debug information. 0 is none, 1
# is minimal, etc. # is minimal, etc.
debug_level = 0 debug_level = 0

24
compiler/sram_base.py
View File

@ -140,11 +140,16 @@ class sram_base(design):
# The order of the control signals on the control bus: # The order of the control signals on the control bus:
self.control_bus_names = [] self.control_bus_names = []
for port in self.all_ports: for port in self.all_ports:
self.control_bus_names[port] = ["clk_buf{}".format(port), "clk_buf_bar{}".format(port)] self.control_bus_names[port] = ["clk_buf{}".format(port)]
if (self.port_id[port] == "rw") or (self.port_id[port] == "w"): wen = "w_en{}".format(port)
self.control_bus_names[port].append("w_en{}".format(port)) sen = "s_en{}".format(port)
if (self.port_id[port] == "rw") or (self.port_id[port] == "r"): pen = "p_en{}".format(port)
self.control_bus_names[port].append("s_en{}".format(port)) if self.port_id[port] == "r":
self.control_bus_names[port].extend([sen, pen])
elif self.port_id[port] == "w":
self.control_bus_names[port].extend([wen])
else:
self.control_bus_names[port].extend([sen, wen, pen])
self.vert_control_bus_positions = self.create_vertical_bus(layer="metal2", self.vert_control_bus_positions = self.create_vertical_bus(layer="metal2",
pitch=self.m2_pitch, pitch=self.m2_pitch,
offset=self.vertical_bus_offset, offset=self.vertical_bus_offset,
@ -287,11 +292,12 @@ class sram_base(design):
temp.append("bank_sel{0}[{1}]".format(port,bank_num)) temp.append("bank_sel{0}[{1}]".format(port,bank_num))
for port in self.read_ports: for port in self.read_ports:
temp.append("s_en{0}".format(port)) temp.append("s_en{0}".format(port))
for port in self.read_ports:
temp.append("p_en{0}".format(port))
for port in self.write_ports: for port in self.write_ports:
temp.append("w_en{0}".format(port)) temp.append("w_en{0}".format(port))
for port in self.all_ports: for port in self.all_ports:
temp.append("clk_buf_bar{0}".format(port)) temp.append("wl_en{0}".format(port))
temp.append("clk_buf{0}".format(port))
temp.extend(["vdd", "gnd"]) temp.extend(["vdd", "gnd"])
self.connect_inst(temp) self.connect_inst(temp)
@ -412,7 +418,9 @@ class sram_base(design):
temp.append("s_en{}".format(port)) temp.append("s_en{}".format(port))
if port in self.write_ports: if port in self.write_ports:
temp.append("w_en{}".format(port)) temp.append("w_en{}".format(port))
temp.extend(["clk_buf_bar{}".format(port), "clk_buf{}".format(port), "vdd", "gnd"]) if port in self.read_ports:
temp.append("p_en{}".format(port))
temp.extend(["wl_en{}".format(port), "clk_buf{}".format(port), "vdd", "gnd"])
self.connect_inst(temp) self.connect_inst(temp)
return insts return insts