Undid change to add bitcell as input to array mod.

compiler/modules/bank.py

@@ -411,8 +411,7 @@ class bank(design.design):
         
         self.bitcell_array = factory.create(module_type="bitcell_array",
                                             cols=self.num_cols,
-                                            rows=self.num_rows,
-                                            bitcell=self.bitcell)
+                                            rows=self.num_rows)
         self.add_mod(self.bitcell_array)
 
         self.precharge_array = []

compiler/modules/bitcell_array.py

@@ -19,14 +19,13 @@ class bitcell_array(design.design):
     and word line is connected by abutment.
     Connects the word lines and bit lines.
     """
-    def __init__(self, cols, rows, name, bitcell):
+    def __init__(self, cols, rows, name):
         design.design.__init__(self, name)
         debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
         self.add_comment("rows: {0} cols: {1}".format(rows, cols))
 
         self.column_size = cols
         self.row_size = rows
-        self.cell = bitcell
 
         self.create_netlist()
         if not OPTS.netlist_only:
@@ -87,6 +86,7 @@ class bitcell_array(design.design):
 
     def add_modules(self):
         """ Add the modules used in this design """
+        self.cell = factory.create(module_type="bitcell")
         self.add_mod(self.cell)
 
     def create_instances(self):

compiler/modules/replica_bitline.py

@@ -88,13 +88,11 @@ class replica_bitline(design.design):
 
         self.replica_bitcell = factory.create(module_type="replica_bitcell")
         self.add_mod(self.replica_bitcell)
-
-        bitcell = factory.create(module_type="bitcell")
+        
         # This is the replica bitline load column that is the height of our array
         self.rbl = factory.create(module_type="bitcell_array",
                                   cols=1,
-                                  rows=self.bitcell_loads,
-                                  bitcell=bitcell)
+                                  rows=self.bitcell_loads)
         self.add_mod(self.rbl)
 
         # FIXME: The FO and depth of this should be tuned