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proper output rom bank output layer

This commit is contained in:
SWalker 2023-10-31 23:23:57 -07:00
parent d161cc55a5
commit ce1861f342
1 changed files with 5 additions and 1 deletions
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6
compiler/modules/rom_bank.py
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@ -427,7 +427,11 @@ class rom_bank(design,rom_verilog):
inv_out_pins = [self.bitline_inv_inst.get_pin("out_{}".format(bl)) for bl in range(self.cols)]
mux_pins = [self.mux_inst.get_pin("bl_{}".format(bl)) for bl in range(self.cols)]
self.connect_col_pins(self.route_stack[2], array_out_pins + inv_in_pins, round=True, directions="nonpref")
if "li" in layer:
output_layer = "m1"
else:
output_layer = "m3"
self.connect_col_pins(output_layer, array_out_pins + inv_in_pins, round=True, directions="nonpref")
self.connect_col_pins(self.interconnect_layer, inv_out_pins + mux_pins, round=True, directions="nonpref")
def route_output_buffers(self):