Merged and addressed conflict in delay.py

compiler/tests/05_bitcell_array_1rw_1r_test.py

@@ -27,8 +27,8 @@ class bitcell_array_1rw_1r_test(openram_test):
         OPTS.num_w_ports = 0
         globals.setup_bitcell()
 
-        debug.info(2, "Testing 4x4 array for cell_1rw_1r")
-        a = factory.create(module_type="bitcell_array", cols=4, rows=4)
+        debug.info(2, "Testing 2x2 array for cell_2port")
+        a = factory.create(module_type="bitcell_array", cols=2, rows=2)
         self.local_check(a)
 
         globals.end_openram()

compiler/tests/14_replica_bitcell_array_test.py

@@ -25,7 +25,7 @@ class replica_bitcell_array_test(openram_test):
 
         factory.reset()
         debug.info(2, "Testing 4x4 array for bitcell")
-        a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 0])
+        a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0])
         self.local_check(a)
 
         globals.end_openram()

compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py

@@ -23,6 +23,7 @@ class sram_1bank_2mux_1rw_1r_test(openram_test):
         globals.init_openram(config_file)
         from sram_config import sram_config
 
+        OPTS.route_supplies = False
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
         OPTS.num_w_ports = 0

compiler/tests/21_model_delay_test.py

@@ -66,7 +66,9 @@ class model_delay_test(openram_test):
 
         # Only compare the delays
         spice_delays = {key:value for key, value in spice_data.items() if 'delay' in key}
+        spice_delays['min_period'] = spice_data['min_period']
         model_delays = {key:value for key, value in model_data.items() if 'delay' in key}
+        model_delays['min_period'] = model_data['min_period']
         debug.info(1,"Spice Delays={}".format(spice_delays))
         debug.info(1,"Model Delays={}".format(model_delays))
 

compiler/tests/26_hspice_pex_pinv_test.py

@@ -17,6 +17,7 @@ from globals import OPTS
 import debug
 
 
+@unittest.skip("SKIPPING 26_hspice_pex_pinv_test")
 class hspice_pex_pinv_test(openram_test):
 
     def runTest(self):
@@ -39,10 +40,10 @@ class hspice_pex_pinv_test(openram_test):
         OPTS.keep_temp =  True
         debug.info(2, "Checking 1x size inverter")
         tx = pinv.pinv(name="pinv", size=1)
-        tempgds = "{0}{1}.gds".format(OPTS.openram_temp, tx.name)
-        tx.gds_write(tempgds)
-        tempsp = "{0}{1}.sp".format(OPTS.openram_temp, tx.name)
-        tx.sp_write(tempsp)
+        tempgds = "{}.gds".format(tx.name)
+        tx.gds_write("{0}{1}".format(OPTS.openram_temp, tempgds))
+        tempsp = "{}.sp".format(tx.name)
+        tx.sp_write("{0}{1}".format(OPTS.openram_temp, tempsp))
 
         # make sure that the library simulation is successful
         sp_delay = self.simulate_delay(test_module=tempsp,
@@ -74,7 +75,7 @@ class hspice_pex_pinv_test(openram_test):
     def simulate_delay(self, test_module, top_level_name):
         from charutils import parse_spice_list
         # setup simulation
-        sim_file = OPTS.openram_temp + "stim.sp"
+        sim_file = "stim.sp"
         log_file_name = "timing"
         test_sim = self.write_simulation(sim_file, test_module, top_level_name)
         test_sim.run_sim("stim.sp")
@@ -86,7 +87,7 @@ class hspice_pex_pinv_test(openram_test):
         import tech
         from characterizer import measurements, stimuli
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
-        sim_file = open(sim_file, "w")
+        sim_file = open(OPTS.openram_temp + sim_file, "w")
         simulation = stimuli(sim_file, corner)
 
         # library files

compiler/tests/26_ngspice_pex_pinv_test.py

@@ -16,7 +16,7 @@ import globals
 from globals import OPTS
 import debug
 
-
+@unittest.skip("SKIPPING 26_ngspice_pex_pinv_test")
 class ngspice_pex_pinv_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -37,10 +37,10 @@ class ngspice_pex_pinv_test(openram_test):
         OPTS.keep_temp = True # force set keep to true to save the sp file
         debug.info(2, "Checking 1x size inverter")
         tx = pinv.pinv(name="pinv", size=1)
-        tempgds = "{0}{1}.gds".format(OPTS.openram_temp, tx.name)
-        tx.gds_write(tempgds)
-        tempsp = "{0}{1}.sp".format(OPTS.openram_temp, tx.name)
-        tx.sp_write(tempsp)
+        tempgds = "{}.gds".format(tx.name)
+        tx.gds_write("{0}{1}".format(OPTS.openram_temp, tempgds))
+        tempsp = "{}.sp".format(tx.name)
+        tx.sp_write("{0}{1}".format(OPTS.openram_temp, tempsp))
 
         # make sure that the library simulation is successful
         sp_delay = self.simulate_delay(test_module=tempsp,
@@ -72,12 +72,17 @@ class ngspice_pex_pinv_test(openram_test):
 
     def simulate_delay(self, test_module, top_level_name):
         from charutils import parse_spice_list
+        cwd = os.getcwd()
+        os.chdir(OPTS.openram_temp)
+
         # setup simulation
-        sim_file = OPTS.openram_temp + "stim.sp"
+        sim_file = "stim.sp"
         log_file_name = "timing"
         test_sim = self.write_simulation(sim_file, test_module, top_level_name)
         test_sim.run_sim("stim.sp")
         delay = parse_spice_list(log_file_name, "pinv_delay")
+        
+        os.chdir(cwd)        
         return delay
 
     def write_simulation(self, sim_file, cir_file, top_module_name):
@@ -89,6 +94,7 @@ class ngspice_pex_pinv_test(openram_test):
         simulation = stimuli(sim_file, corner)
 
         # library files
+        import pdb; pdb.set_trace()
         simulation.write_include(cir_file)
 
         # supply voltages

compiler/tests/30_openram_back_end_test.py

@@ -53,21 +53,27 @@ class openram_back_end_test(openram_test):
         else:
             exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME)
         config_name = "{0}/tests/configs/config_back_end.py".format(OPENRAM_HOME)
-        cmd = "{0} -n -o {1} -p {2} {3} {4} 2>&1 > {5}/output.log".format(exe_name,
-                                                                          out_file,
-                                                                          out_path,
-                                                                          options,
-                                                                          config_name,
-                                                                          out_path)
+        cmd = "{0} -o {1} -p {2} {3} {4} 2>&1 > {5}/output.log".format(exe_name,
+                                                                       out_file,
+                                                                       out_path,
+                                                                       options,
+                                                                       config_name,
+                                                                       out_path)
         debug.info(1, cmd)
         os.system(cmd)
 
         # assert an error until we actually check a resul
-        for extension in ["gds", "v", "lef", "sp"]:
-            filename = "{0}/{1}.{2}".format(out_path, out_file, extension)
+        for extension in ["gds", "v", "lef", "sp", "lvs.sp"]:
+            filename = "{0}{1}.{2}".format(out_path, out_file, extension)
             debug.info(1, "Checking for file: " + filename)
             self.assertEqual(os.path.exists(filename), True)
 
+        # check if the auxiliary scripts were created
+        for out_file in ["run_drc.sh", "run_lvs.sh"]:
+            filename = "{0}{1}".format(out_path, out_file)
+            debug.info(1, "Checking for file: " + filename)
+            self.assertEqual(os.path.exists(filename), True)
+            
         # Make sure there is any .lib file
         import glob
         files = glob.glob('{0}/*.lib'.format(out_path))
@@ -79,7 +85,7 @@ class openram_back_end_test(openram_test):
             self.assertTrue(len(datasheets)>0)
 
         # grep any errors from the output
-        output_log = open("{0}/output.log".format(out_path), "r")
+        output_log = open("{0}output.log".format(out_path), "r")
         output = output_log.read()
         output_log.close()
         self.assertEqual(len(re.findall('ERROR', output)), 0)

compiler/tests/configs/config.py

@@ -12,6 +12,5 @@ num_words = 16
 tech_name = OPTS.tech_name
 
 nominal_corner_only = True
-route_supplies = True
 check_lvsdrc = True
 

compiler/tests/configs/config_back_end.py

@@ -12,9 +12,7 @@ num_words = 16
 tech_name = OPTS.tech_name
 
 nominal_corner_only = True
-route_supplies = True
 check_lvsdrc = True
-inline_lvsdrc = True
-analytical_delay = False
+spice_name = "ngspice"
 
 

compiler/tests/skip_tests_sky130.txt

@@ -3,7 +3,6 @@
 04_precharge_pbitcell_test.py
 04_replica_pbitcell_test.py
 04_column_mux_pbitcell_test.py
-05_bitcell_1rw_1r_array_test.py
 05_bitcell_array_test.py
 05_dummy_array_test.py
 05_pbitcell_array_test.py

compiler/tests/testutils.py

@@ -21,8 +21,8 @@ class openram_test(unittest.TestCase):
 
         self.reset()
 
-        tempgds = "{0}{1}.gds".format(OPTS.openram_temp, w.name)
-        w.gds_write(tempgds)
+        tempgds = "{}.gds".format(w.name)
+        w.gds_write("{0}{1}".format(OPTS.openram_temp, tempgds))
         import verify
 
         result=verify.run_drc(w.name, tempgds, None)
@@ -36,13 +36,13 @@ class openram_test(unittest.TestCase):
 
         self.reset()
 
-        tempspice = "{0}{1}.sp".format(OPTS.openram_temp, a.name)
-        tempgds = "{0}{1}.gds".format(OPTS.openram_temp, a.name)
+        tempspice = "{}.sp".format(a.name)
+        tempgds = "{}.gds".format(a.name)
 
-        a.lvs_write(tempspice)
+        a.lvs_write("{0}{1}".format(OPTS.openram_temp, tempspice))
         # cannot write gds in netlist_only mode
         if not OPTS.netlist_only:
-            a.gds_write(tempgds)
+            a.gds_write("{0}{1}".format(OPTS.openram_temp, tempgds))
 
             import verify
             # Run both DRC and LVS even if DRC might fail
@@ -80,15 +80,13 @@ class openram_test(unittest.TestCase):
             self.cleanup()
 
     def run_pex(self, a, output=None):
-        if output == None:
-            output = OPTS.openram_temp + a.name + ".pex.netlist"
-        tempspice = "{0}{1}.sp".format(OPTS.openram_temp, a.name)
-        tempgds = "{0}{1}.gds".format(OPTS.openram_temp, a.name)
+        tempspice = "{}.sp".format(a.name)
+        tempgds = "{}.gds".format(a.name)
 
-        a.gds_write(tempgds)
+        a.gds_write("{0}{1}".format(OPTS.openram_temp, tempgds))
 
         import verify
-        result=verify.run_pex(a.name, tempgds, tempspice, output=output, final_verification=False)
+        result=verify.run_pex(a.name, tempgds, tempspice, final_verification=False)
         if result != 0:
             self.fail("PEX ERROR: {}".format(a.name))
         return output