mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-03 08:27:11 +02:00
Added some data scaling and error calculation in model check.
This commit is contained in:
@@ -62,6 +62,7 @@ class openram_test(unittest.TestCase):
|
||||
delay_obj.set_load_slew(load, slew)
|
||||
delay_obj.set_probe(probe_address="1"*sram.addr_size, probe_data=(sram.word_size-1))
|
||||
test_port = delay_obj.read_ports[0] #Only test one port, assumes other ports have similar period.
|
||||
delay_obj.create_measurement_objects()
|
||||
delay_obj.find_feasible_period_one_port(test_port)
|
||||
return delay_obj.period
|
||||
|
||||
|
||||
Reference in New Issue
Block a user