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spacing tweaks for gf180 address control gate

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This commit is contained in:
Sage Walker
2023-10-31 23:24:21 -07:00
committed by SWalker
parent d940c0e03d
commit cb8567c66f
5 changed files with 50 additions and 31 deletions
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compiler/modules/pinv_dec.py
+4 -2
View File
@@ -242,10 +242,12 @@ class pinv_dec(pinv):
source_pos = self.nmos_inst.get_pin("S").center()
self.add_via_stack_center(offset=source_pos,
from_layer=self.route_layer,
to_layer=self.supply_layer)
to_layer=self.supply_layer,
min_area=True)
source_pos = self.pmos_inst.get_pin("S").center()
self.add_via_stack_center(offset=source_pos,
from_layer=self.route_layer,
to_layer=self.supply_layer)
to_layer=self.supply_layer,
min_area=True)
compiler/modules/rom_address_control_array.py
+3 -2
View File
@@ -21,11 +21,11 @@ class rom_address_control_array(design):
self.size=inv_size
self.cols = cols
self.route_layer = route_layer
dff = factory.create(module_type="dff")
if name=="":
name = "rom_inv_array_{0}".format(cols)
if inv_height == None:
self.inv_height = dff.height * 0.5
self.inv_height = drc("minwidth_{}".format(route_layer)) * 14
else:
self.inv_height = inv_height
@@ -34,6 +34,7 @@ class rom_address_control_array(design):
self.inv_layer = "li"
else:
self.inv_layer = "m1"
self.route_layer = "m2"
super().__init__(name)
self.create_netlist()
self.create_layout()
compiler/modules/rom_address_control_buf.py
+20 -13
View File
@@ -25,8 +25,11 @@ class rom_address_control_buf(design):
self.size = size
if "li" in layer:
self.inv_layer = "li"
self.non_inverting_layer = "m2"
else:
self.inv_layer = "m1"
self.route_layer = "m2"
self.non_inverting_layer = "m3"
super().__init__(name)
self.create_netlist()
self.create_layout()
@@ -47,11 +50,11 @@ class rom_address_control_buf(design):
def create_modules(self):
self.inv = factory.create(module_type="pinv_dec", module_name="inv_array_mod", add_wells=False, size=self.size)
self.nand = factory.create(module_type="nand2_dec", height=self.inv.height)
# For layout constants
self.cell = factory.create(module_type="rom_base_cell")
self.nand = factory.create(module_type="nand2_dec")
self.inv = factory.create(module_type="pinv_dec", module_name="inv_array_mod", add_wells=False, size=self.size, height=self.nand.height)
def add_pins(self):
self.add_pin("A_in", "INPUT")
@@ -129,18 +132,18 @@ class rom_address_control_buf(design):
# Route first NAND output to second NAND input
start = A_out.center()
end = Aint_in.center()
self.add_path("m2", [start, end])
self.add_via_stack_center(Aint_in.center(), self.inv_layer, "m2")
self.add_via_stack_center(A_out.center(), self.inv_layer, "m2")
self.add_path(self.non_inverting_layer, [start, end])
self.add_via_stack_center(Aint_in.center(), self.inv_layer, self.non_inverting_layer)
self.add_via_stack_center(A_out.center(), self.inv_layer, self.non_inverting_layer)
# Route first NAND to output pin
self.add_segment_center("m2", end, vector(end.x, self.addr_bar_nand.uy()))
self.add_layout_pin_rect_center("A_out", offset=vector(end.x, self.addr_bar_nand.uy() - 0.5 * self.m2_width), layer="m2")
self.add_segment_center(self.non_inverting_layer, end, vector(end.x, self.addr_bar_nand.uy()))
self.add_layout_pin_rect_center("A_out", offset=vector(end.x, self.addr_bar_nand.uy() - 0.5 * self.m2_width), layer=self.non_inverting_layer)
# Route second NAND to output pin
self.add_via_stack_center(Abar_out.center(), self.inv_layer, "m2")
self.add_segment_center("m2", Abar_out.center(), vector(Abar_out.cx(), self.addr_bar_nand.uy()))
self.add_layout_pin_rect_center("Abar_out", offset=vector(Abar_out.cx(), self.addr_bar_nand.uy() - 0.5 * self.m2_width), layer="m2")
self.add_via_stack_center(Abar_out.center(), self.inv_layer, self.non_inverting_layer)
self.add_segment_center(self.non_inverting_layer, Abar_out.center(), vector(Abar_out.cx(), self.addr_bar_nand.uy()))
self.add_layout_pin_rect_center("Abar_out", offset=vector(Abar_out.cx(), self.addr_bar_nand.uy() - 0.5 * self.m2_width), layer=self.non_inverting_layer)
# Route inverter output to NAND
end = vector(Abar_int_out.cx(), Abar_in.cy() + 0.5 * self.interconnect_width)
@@ -166,14 +169,17 @@ class rom_address_control_buf(design):
left_edge = self.inv_inst.get_pin("Z").cx() - 2 * self.contact_width - 2 * self.active_contact_to_gate - 4 * self.active_enclose_contact - self.poly_width - self.active_space
contact_pos = vector(left_edge, source_pin.cy())
self.add_layout_pin_rect_center("left_edge", offset=contact_pos, layer="m1")
self.add_via_center(layers=self.active_stack,
offset=contact_pos,
implant_type="n",
well_type="n")
self.add_via_stack_center(offset=contact_pos,
from_layer=self.active_stack[2],
to_layer=self.route_layer)
to_layer=self.route_layer,
min_area=True)
# self.add_segment_center(layer=self.)
contact_pos = vector(left_edge, gnd_pin.cy())
self.add_via_center(layers=self.active_stack,
@@ -182,4 +188,5 @@ class rom_address_control_buf(design):
well_type="p")
self.add_via_stack_center(offset=contact_pos,
from_layer=self.active_stack[2],
to_layer=self.route_layer)
to_layer=self.route_layer,
min_area=True)