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This commit is contained in:
Jesse Cirimelli-Low
2026-04-22 01:33:47 -07:00
parent 5fd548582f
commit cb7f117daa
18 changed files with 1768 additions and 39 deletions
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compiler/modules/bitcell_base_array.py
+4 -3
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@@ -121,13 +121,14 @@ class bitcell_base_array(design):
def get_all_wordline_names(self, port=None):
""" Return all the wordline names """
temp = []
temp.extend(self.get_rbl_wordline_names(0))
if len(self.all_ports) > 1:
temp.extend(self.get_rbl_wordline_names(1))
if port == None:
temp.extend(self.all_wordline_names)
else:
temp.extend(self.wordline_names[port])
if len(self.all_ports) > 1:
temp.extend(self.get_rbl_wordline_names(1))
temp.extend(self.get_rbl_wordline_names(0))
return temp
def add_bitline_pins(self):