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@@ -25,6 +25,7 @@ class bitcell_base(design):
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self.nets_match = self.do_nets_exist(prop.storage_nets)
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self.mirror = prop.mirror
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self.end_caps = prop.end_caps
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self.has_corners = prop.has_corners
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def get_stage_effort(self, load):
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parasitic_delay = 1
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# This accounts for bitline being drained
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