squash commits

compiler/modules/bitcell_array.py

@@ -72,8 +72,8 @@ class bitcell_array(bitcell_base_array):
             core_block = [[0 for x in range(1)] for y in range(2)] 
             core_block[(0 + self.row_offset) % 2][(0+self.column_offset) %2] = geometry.instance("core_0_0", mod=self.cell, is_bitcell=True)
             core_block[(1 + self.row_offset) % 2][(0+self.column_offset) %2] = geometry.instance("core_1_0", mod=self.cell, is_bitcell=True, mirror='MX')
-        print(r, c)
-        print(core_block)
+        #print(r, c)
+        #print(core_block)
 
         self.pattern = pattern(self, "bitcell_array", core_block, num_rows=self.row_size, num_cols=self.column_size,name_template="bit_r{0}_c{1}")
         self.pattern.connect_array()

compiler/modules/bitcell_base.py

@@ -25,6 +25,7 @@ class bitcell_base(design):
             self.nets_match = self.do_nets_exist(prop.storage_nets)
             self.mirror = prop.mirror
             self.end_caps = prop.end_caps
+            self.has_corners = prop.has_corners
     def get_stage_effort(self, load):
         parasitic_delay = 1
         # This accounts for bitline being drained

compiler/modules/bitcell_base_array.py

@@ -121,13 +121,14 @@ class bitcell_base_array(design):
     def get_all_wordline_names(self, port=None):
         """ Return all the wordline names """
         temp = []
-        temp.extend(self.get_rbl_wordline_names(0))
+        if len(self.all_ports) > 1:
+            temp.extend(self.get_rbl_wordline_names(1))
         if port == None:
             temp.extend(self.all_wordline_names)
         else:
             temp.extend(self.wordline_names[port])
-        if len(self.all_ports) > 1:
-            temp.extend(self.get_rbl_wordline_names(1))
+        temp.extend(self.get_rbl_wordline_names(0))
+
         return temp
 
     def add_bitline_pins(self):

compiler/modules/capped_replica_bitcell_array.py

@@ -86,7 +86,7 @@ class capped_replica_bitcell_array(bitcell_base_array):
                                           rows=1,
                                           # dummy column + left replica column(s)
                                           column_offset=1,
-                                          row_offset=self.row_size+ self.extra_rows,
+                                          row_offset=self.row_size+ self.extra_rows + 1, #add 1 to account for bottom col_cap
                                           mirror=0,
                                           location="top",
                                           left_rbl=self.left_rbl,
@@ -162,10 +162,21 @@ class capped_replica_bitcell_array(bitcell_base_array):
         self.unused_wordline_names = self.replica_bitcell_array.unused_wordline_names
         self.replica_array_wordline_names_with_grounded_wls = ["gnd" if x in self.unused_wordline_names else x for x in self.replica_bitcell_array.wordline_pin_list]
 
+        # Left/right row caps cover the full array height. Pad with gnd so the
+        # netlist list length matches the row cap (replica in the center); do
+        # not use col cap wordline heuristics.
+
+        n_rowcap_wl = len(self.row_cap_left.get_wordline_names())
+        n_rba_wl = len(self.replica_array_wordline_names_with_grounded_wls)
+
+
         self.wordline_pin_list = []
-        self.wordline_pin_list.extend(["gnd"] * len(self.col_cap_top.get_wordline_names()))
+
+        if self.rbls:
+            self.wordline_pin_list.extend(["gnd"] * len(self.rbls))
         self.wordline_pin_list.extend(self.replica_array_wordline_names_with_grounded_wls)
-        self.wordline_pin_list.extend(["gnd"] * len(self.col_cap_bottom.get_wordline_names()))
+        if self.rbls:
+            self.wordline_pin_list.extend(["gnd"] * len(self.rbls))
 
         self.add_pin_list(self.used_wordline_names, "INPUT")
 
@@ -192,6 +203,10 @@ class capped_replica_bitcell_array(bitcell_base_array):
         self.dummy_col_insts.append(self.add_inst(name="dummy_col_left",
                                                     mod=self.row_cap_left))
         self.connect_inst(["dummy_left_" + bl for bl in self.row_cap_left.all_bitline_names] + self.wordline_pin_list + self.supplies)
+
+        #print(self.dummy_col_insts[0].mod.pins)
+        #print(["dummy_left_" + bl for bl in self.row_cap_left.all_bitline_names] + self.wordline_pin_list + self.supplies)
+
         self.dummy_col_insts.append(self.add_inst(name="dummy_col_right",
                                                     mod=self.row_cap_right))
         self.connect_inst(["dummy_right_" + bl for bl in self.row_cap_right.all_bitline_names] + self.wordline_pin_list + self.supplies)
@@ -282,10 +297,14 @@ class capped_replica_bitcell_array(bitcell_base_array):
         # Far left dummy col
         dummy_col_width =  vector(self.dummy_col_insts[0].width, 0)
         offset = self.dummy_row_insts[0].ll() - dummy_col_width
+        if self.dummy_col_insts[0].mod.cell.has_corners is False:
+            offset += vector(0, dummy_row_height.y)
         self.dummy_col_insts[0].place(offset=offset)
 
         # Far right dummy col
         offset = self.dummy_row_insts[0].lr()
+        if self.dummy_col_insts[0].mod.cell.has_corners is False:
+            offset += vector(0, dummy_row_height.y)
         self.dummy_col_insts[1].place(offset=offset)
 
     def add_layout_pins(self):

compiler/modules/col_cap_array.py

@@ -15,7 +15,7 @@ class col_cap_array(bitcell_base_array):
     Generate a dummy row/column for the replica array.
     """
     def __init__(self, rows, cols, column_offset=0, row_offset=0, mirror=0, location="", name="",left_rbl=[],right_rbl=[]):
-        super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
+        super().__init__(rows=rows, cols=cols, column_offset=column_offset, row_offset=row_offset, name=name)
         self.mirror = mirror
         self.location = location
 

compiler/modules/dummy_array.py

@@ -67,8 +67,8 @@ class dummy_array(bitcell_base_array):
             core_block = [[0 for x in range(1)] for y in range(2)] 
             core_block[(0 + self.row_offset) % 2][(0+self.column_offset) %2] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True)
             core_block[(1 + self.row_offset) % 2][(0+self.column_offset) %2] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True, mirror='MX')
-        print(r, c)
-        print(core_block)
+        #print(r, c)
+        #print(core_block)
 
         self.pattern = pattern(self, "dummy_array", core_block, num_rows=self.row_size, num_cols=self.column_size, name_template="bit_r{0}_c{1}")
         self.pattern.connect_array()

compiler/modules/pattern.py

@@ -182,7 +182,7 @@ class pattern():
             y += inst.height
         if "Y" in inst.mirror:
             x += inst.width
-        print('placing inst {} at {}'.format(inst, offset))
+        #print('placing inst {} at {}'.format(inst, offset))
         inst.place((x, y), inst.mirror, inst.rotate)
 
     def place_array(self):

compiler/modules/replica_bitcell_array.py

@@ -76,8 +76,8 @@ class replica_bitcell_array(bitcell_base_array):
         """  Array and dummy/replica columns """
         # Bitcell array
         self.bitcell_array = factory.create(module_type="bitcell_array",
-                                            column_offset=len(self.left_rbl),
-                                            row_offset=len(self.left_rbl),
+                                            column_offset=len(self.left_rbl)+ 1, #add 1 to account for left row_cap
+                                            row_offset=len(self.left_rbl)+1, #add 1 to account for bottom col_cap
                                             cols=self.column_size,
                                             rows=self.row_size,
                                             left_rbl=self.left_rbl, 
@@ -92,11 +92,11 @@ class replica_bitcell_array(bitcell_base_array):
             if port in self.left_rbl:
                 # These go top down starting from the bottom of the bitcell array.
                 replica_bit = self.rbl[0] - port - 1
-                column_offset = 0
+                column_offset = 1
             elif port in self.right_rbl:
                 # These go bottom up starting from the top of the bitcell array.
                 replica_bit = self.rbl[0] + self.row_size + port - 1
-                column_offset = len(self.left_rbl) + self.column_size
+                column_offset = len(self.left_rbl) + self.column_size + 1
             else:
                 continue
 
@@ -120,8 +120,8 @@ class replica_bitcell_array(bitcell_base_array):
             self.dummy_rows[port] = factory.create(module_type="dummy_array",
                                             cols=self.column_size,
                                             rows=1,
-                                            row_offset=row_offset,
-                                            column_offset=len(self.left_rbl))
+                                            row_offset=row_offset+1, #add 1 to account for bottom col_cap
+                                            column_offset=len(self.left_rbl)+1) #add 1 to account for left row_cap
 
     def add_pins(self):
 

compiler/modules/replica_column.py

@@ -96,14 +96,14 @@ class replica_column(bitcell_base_array):
             # All other cells are dummies
             if (row == self.replica_bit) or (row >= self.row_start and row < self.row_end):
                 if current_row % 2 == 0:
-                    core_block[row][0] = geometry.instance("rbc_{}".format(row), mod=self.replica_cell, is_bitcell=True)
-                else:
                     core_block[row][0] = geometry.instance("rbc_{}".format(row), mod=self.replica_cell, is_bitcell=True, mirror='MX')
+                else:
+                    core_block[row][0] = geometry.instance("rbc_{}".format(row), mod=self.replica_cell, is_bitcell=True)
             else:
                 if current_row % 2 == 0:
-                    core_block[row][0] = geometry.instance("rbc_{}".format(row), mod=self.dummy_cell, is_bitcell=True)
-                else:
                     core_block[row][0] = geometry.instance("rbc_{}".format(row), mod=self.dummy_cell, is_bitcell=True, mirror='MX')
+                else:
+                    core_block[row][0] = geometry.instance("rbc_{}".format(row), mod=self.dummy_cell, is_bitcell=True)
 
             current_row += 1
             

compiler/modules/row_cap_array.py

@@ -15,7 +15,7 @@ class row_cap_array(bitcell_base_array):
     Generate a dummy row/column for the replica array.
     """
     def __init__(self, rows, cols, column_offset=0, row_offset=0, mirror=0, location="", name=""):
-        super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
+        super().__init__(rows=rows, cols=cols, column_offset=column_offset, row_offset=row_offset, name=name)
         self.mirror = mirror
         self.location = location
         self.row_offset = row_offset
@@ -76,7 +76,11 @@ class row_cap_array(bitcell_base_array):
                     pattern.append_row_to_block(bit_block, [rowend_m])
 
         #pattern.append_row_to_block(bit_block, [bottom_corner])
-        self.pattern = pattern(self, "row_cap_array_" + self.location, bit_block, num_rows=self.row_size, num_cols=self.column_size, num_cores_x=ceil(self.column_size/2), num_cores_y=ceil(self.row_size/2), name_template="row_cap_array" + self.location + "_r{0}_c{1}")
+        if self.cell.has_corners is False:
+            num_rows = self.row_size - 2
+        else:
+            num_rows = self.row_size
+        self.pattern = pattern(self, "row_cap_array_" + self.location, bit_block, num_rows=num_rows, num_cols=self.column_size, num_cores_x=ceil(self.column_size/2), num_cores_y=ceil(self.row_size/2), name_template="row_cap_array" + self.location + "_r{0}_c{1}")
         self.pattern.connect_array_raw()
 
     def get_bitcell_pins(self, row, col):