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Added 1bank module check to the multibank test

This commit is contained in:
Bugra Onal 2022-07-21 15:39:23 -07:00
parent 3f1a5a2051
commit caac39c88b
1 changed files with 10 additions and 3 deletions
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13
compiler/tests/25_verilog_multibank_test.py
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@ -37,15 +37,22 @@ class multibank_verilog_test(openram_test):
vfile = s.name + ".v" vfile = s.name + ".v"
vname = OPTS.openram_temp + vfile vname = OPTS.openram_temp + vfile
v1bfile = s.name + "_1bank.v"
v1bname = OPTS.openram_temp + v1bfile
s.verilog_write(vname) s.verilog_write(vname)
# let's diff the result with a golden model # let's diff the result with a golden model
golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)), vfile) multi_golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)), vfile)
self.assertTrue(self.isdiff(vname, golden)) self.assertTrue(self.isdiff(vname, multi_golden))
one_golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)), v1bname)
self.assertTrue(self.isdiff(v1bname, one_golden))
globals.end_openram() globals.end_openram()
# run the test from the command line # run the test from the command line
if __name__ == "__main__": if __name__ == "__main__":
(OPTS, args) = globals.parse_args() (OPTS, args) = globals.parse_args()