mirror of https://github.com/VLSIDA/OpenRAM.git
Convert supply to wider DRC rules
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parent
49f7022416
commit
c6f03e70d4
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@ -13,8 +13,8 @@ class options(optparse.Values):
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# This is the name of the technology.
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# This is the name of the technology.
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tech_name = ""
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tech_name = ""
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# This is the temp directory where all intermediate results are stored.
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# This is the temp directory where all intermediate results are stored.
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openram_temp = "/tmp/openram_{0}_{1}_temp/".format(getpass.getuser(),os.getpid())
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#openram_temp = "/tmp/openram_{0}_{1}_temp/".format(getpass.getuser(),os.getpid())
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#openram_temp = "{0}/openram_temp/".format(os.getenv("HOME"))
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openram_temp = "{0}/openram_temp/".format(os.getenv("HOME"))
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# This is the verbosity level to control debug information. 0 is none, 1
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# This is the verbosity level to control debug information. 0 is none, 1
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# is minimal, etc.
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# is minimal, etc.
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debug_level = 0
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debug_level = 0
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@ -3,12 +3,13 @@ from contact import contact
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from pin_group import pin_group
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from pin_group import pin_group
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from vector import vector
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from vector import vector
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import debug
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import debug
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import math
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class router_tech:
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class router_tech:
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"""
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"""
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This is a class to hold the router tech constants.
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This is a class to hold the router tech constants.
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"""
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"""
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def __init__(self, layers):
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def __init__(self, layers, supply_router=False):
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"""
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"""
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Allows us to change the layers that we are routing on. First layer
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Allows us to change the layers that we are routing on. First layer
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is always horizontal, middle is via, and last is always
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is always horizontal, middle is via, and last is always
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@ -16,35 +17,42 @@ class router_tech:
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"""
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"""
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self.layers = layers
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self.layers = layers
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(self.horiz_layer_name, self.via_layer_name, self.vert_layer_name) = self.layers
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(self.horiz_layer_name, self.via_layer_name, self.vert_layer_name) = self.layers
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# This is the minimum routed track spacing
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# This is the minimum routed track spacing
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via_connect = contact(self.layers, (1, 1))
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via_connect = contact(self.layers, (1, 1))
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self.max_via_size = max(via_connect.width,via_connect.height)
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max_via_size = max(via_connect.width,via_connect.height)
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self.vert_layer_minwidth = drc("minwidth_{0}".format(self.vert_layer_name))
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self.horiz_layer_number = layer[self.horiz_layer_name]
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self.vert_layer_spacing = drc(str(self.vert_layer_name)+"_to_"+str(self.vert_layer_name))
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self.vert_layer_number = layer[self.vert_layer_name]
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self.vert_layer_number = layer[self.vert_layer_name]
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self.horiz_layer_minwidth = drc("minwidth_{0}".format(self.horiz_layer_name))
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if supply_router:
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self.horiz_layer_spacing = drc(str(self.horiz_layer_name)+"_to_"+str(self.horiz_layer_name))
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(self.vert_layer_minwidth, self.vert_layer_spacing) = self.get_supply_layer_width_space(1,2)
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self.horiz_layer_number = layer[self.horiz_layer_name]
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(self.horiz_layer_minwidth, self.horiz_layer_spacing) = self.get_supply_layer_width_space(0,2)
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self.horiz_track_width = self.max_via_size + self.horiz_layer_spacing
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self.vert_track_width = self.max_via_size + self.vert_layer_spacing
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# For supplies, we will make the wire wider than the vias
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self.vert_layer_minwidth = max(self.vert_layer_minwidth, max_via_size)
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self.horiz_layer_minwidth = max(self.horiz_layer_minwidth, max_via_size)
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self.horiz_track_width = self.horiz_layer_minwidth + self.horiz_layer_spacing
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self.vert_track_width = self.vert_layer_minwidth + self.vert_layer_spacing
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else:
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(self.vert_layer_minwidth, self.vert_layer_spacing) = self.get_layer_width_space(1)
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(self.horiz_layer_minwidth, self.horiz_layer_spacing) = self.get_layer_width_space(0)
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self.horiz_track_width = max_via_size + self.horiz_layer_spacing
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self.vert_track_width = max_via_size + self.vert_layer_spacing
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# We'll keep horizontal and vertical tracks the same for simplicity.
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# We'll keep horizontal and vertical tracks the same for simplicity.
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self.track_width = max(self.horiz_track_width,self.vert_track_width)
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self.track_width = max(self.horiz_track_width,self.vert_track_width)
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debug.info(1,"Track width: "+str(self.track_width))
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debug.info(1,"Track width: "+str(self.track_width))
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self.track_widths = vector([self.track_width] * 2)
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self.track_widths = vector([self.track_width] * 2)
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self.track_factor = vector([1/self.track_width] * 2)
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self.track_factor = vector([1/self.track_width] * 2)
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debug.info(2,"Track factor: {0}".format(self.track_factor))
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debug.info(2,"Track factor: {0}".format(self.track_factor))
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# When we actually create the routes, make them the width of the track (minus 1/2 spacing on each side)
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# When we actually create the routes, make them the width of the track (minus 1/2 spacing on each side)
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self.layer_widths = [self.track_width - self.horiz_layer_spacing, 1, self.track_width - self.vert_layer_spacing]
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self.layer_widths = [self.track_width - self.horiz_layer_spacing, 1, self.track_width - self.vert_layer_spacing]
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def get_zindex(self,layer_num):
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def get_zindex(self,layer_num):
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if layer_num==self.horiz_layer_number:
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if layer_num==self.horiz_layer_number:
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return 0
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return 0
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@ -76,4 +84,24 @@ class router_tech:
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return (min_width,min_spacing)
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return (min_width,min_spacing)
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def get_supply_layer_width_space(self, zindex, widths=2):
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"""
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These are the width and spacing of a supply layer given a supply rail
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of the given number of min wire widths.
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"""
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if zindex==1:
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layer_name = self.vert_layer_name
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elif zindex==0:
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layer_name = self.horiz_layer_name
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else:
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debug.error("Invalid zindex for track", -1)
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wire_width = widths*drc("minwidth_{0}".format(layer_name), 0, math.inf)
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min_width = drc("minwidth_{0}".format(layer_name), wire_width, math.inf)
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min_spacing = drc(str(layer_name)+"_to_"+str(layer_name), wire_width, math.inf)
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return (min_width,min_spacing)
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@ -72,7 +72,7 @@ class supply_router(router):
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#start_time = datetime.now()
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#start_time = datetime.now()
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self.find_pins_and_blockages([self.vdd_name, self.gnd_name])
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self.find_pins_and_blockages([self.vdd_name, self.gnd_name])
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#print_time("Pins and blockages",datetime.now(), start_time)
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#print_time("Pins and blockages",datetime.now(), start_time)
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#self.write_debug_gds("pin_enclosures.gds",stop_program=True)
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self.write_debug_gds("pin_enclosures.gds",stop_program=True)
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# Add the supply rails in a mesh network and connect H/V with vias
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# Add the supply rails in a mesh network and connect H/V with vias
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#start_time = datetime.now()
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#start_time = datetime.now()
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@ -248,8 +248,8 @@ class supply_router(router):
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rail_width = self.track_width*self.rail_track_width
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rail_width = self.track_width*self.rail_track_width
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# Get the conservative width and spacing of the top rails
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# Get the conservative width and spacing of the top rails
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(horizontal_width, horizontal_space) = self.get_layer_width_space(0, rail_width, rail_length)
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(horizontal_width, horizontal_space) = self.get_supply_layer_width_space(0,2)
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(vertical_width, vertical_space) = self.get_layer_width_space(1, rail_width, rail_length)
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(vertical_width, vertical_space) = self.get_supply_layer_width_space(1,2)
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width = max(horizontal_width, vertical_width)
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width = max(horizontal_width, vertical_width)
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space = max(horizontal_space, vertical_space)
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space = max(horizontal_space, vertical_space)
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