Convert supply to wider DRC rules

This commit is contained in:
Matt Guthaus 2018-12-03 11:09:17 -08:00
parent 49f7022416
commit c6f03e70d4
3 changed files with 49 additions and 21 deletions

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@ -13,8 +13,8 @@ class options(optparse.Values):
# This is the name of the technology. # This is the name of the technology.
tech_name = "" tech_name = ""
# This is the temp directory where all intermediate results are stored. # This is the temp directory where all intermediate results are stored.
openram_temp = "/tmp/openram_{0}_{1}_temp/".format(getpass.getuser(),os.getpid()) #openram_temp = "/tmp/openram_{0}_{1}_temp/".format(getpass.getuser(),os.getpid())
#openram_temp = "{0}/openram_temp/".format(os.getenv("HOME")) openram_temp = "{0}/openram_temp/".format(os.getenv("HOME"))
# This is the verbosity level to control debug information. 0 is none, 1 # This is the verbosity level to control debug information. 0 is none, 1
# is minimal, etc. # is minimal, etc.
debug_level = 0 debug_level = 0

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@ -3,12 +3,13 @@ from contact import contact
from pin_group import pin_group from pin_group import pin_group
from vector import vector from vector import vector
import debug import debug
import math
class router_tech: class router_tech:
""" """
This is a class to hold the router tech constants. This is a class to hold the router tech constants.
""" """
def __init__(self, layers): def __init__(self, layers, supply_router=False):
""" """
Allows us to change the layers that we are routing on. First layer Allows us to change the layers that we are routing on. First layer
is always horizontal, middle is via, and last is always is always horizontal, middle is via, and last is always
@ -16,35 +17,42 @@ class router_tech:
""" """
self.layers = layers self.layers = layers
(self.horiz_layer_name, self.via_layer_name, self.vert_layer_name) = self.layers (self.horiz_layer_name, self.via_layer_name, self.vert_layer_name) = self.layers
# This is the minimum routed track spacing # This is the minimum routed track spacing
via_connect = contact(self.layers, (1, 1)) via_connect = contact(self.layers, (1, 1))
self.max_via_size = max(via_connect.width,via_connect.height) max_via_size = max(via_connect.width,via_connect.height)
self.vert_layer_minwidth = drc("minwidth_{0}".format(self.vert_layer_name)) self.horiz_layer_number = layer[self.horiz_layer_name]
self.vert_layer_spacing = drc(str(self.vert_layer_name)+"_to_"+str(self.vert_layer_name))
self.vert_layer_number = layer[self.vert_layer_name] self.vert_layer_number = layer[self.vert_layer_name]
self.horiz_layer_minwidth = drc("minwidth_{0}".format(self.horiz_layer_name)) if supply_router:
self.horiz_layer_spacing = drc(str(self.horiz_layer_name)+"_to_"+str(self.horiz_layer_name)) (self.vert_layer_minwidth, self.vert_layer_spacing) = self.get_supply_layer_width_space(1,2)
self.horiz_layer_number = layer[self.horiz_layer_name] (self.horiz_layer_minwidth, self.horiz_layer_spacing) = self.get_supply_layer_width_space(0,2)
self.horiz_track_width = self.max_via_size + self.horiz_layer_spacing
self.vert_track_width = self.max_via_size + self.vert_layer_spacing
# For supplies, we will make the wire wider than the vias
self.vert_layer_minwidth = max(self.vert_layer_minwidth, max_via_size)
self.horiz_layer_minwidth = max(self.horiz_layer_minwidth, max_via_size)
self.horiz_track_width = self.horiz_layer_minwidth + self.horiz_layer_spacing
self.vert_track_width = self.vert_layer_minwidth + self.vert_layer_spacing
else:
(self.vert_layer_minwidth, self.vert_layer_spacing) = self.get_layer_width_space(1)
(self.horiz_layer_minwidth, self.horiz_layer_spacing) = self.get_layer_width_space(0)
self.horiz_track_width = max_via_size + self.horiz_layer_spacing
self.vert_track_width = max_via_size + self.vert_layer_spacing
# We'll keep horizontal and vertical tracks the same for simplicity. # We'll keep horizontal and vertical tracks the same for simplicity.
self.track_width = max(self.horiz_track_width,self.vert_track_width) self.track_width = max(self.horiz_track_width,self.vert_track_width)
debug.info(1,"Track width: "+str(self.track_width)) debug.info(1,"Track width: "+str(self.track_width))
self.track_widths = vector([self.track_width] * 2) self.track_widths = vector([self.track_width] * 2)
self.track_factor = vector([1/self.track_width] * 2) self.track_factor = vector([1/self.track_width] * 2)
debug.info(2,"Track factor: {0}".format(self.track_factor)) debug.info(2,"Track factor: {0}".format(self.track_factor))
# When we actually create the routes, make them the width of the track (minus 1/2 spacing on each side) # When we actually create the routes, make them the width of the track (minus 1/2 spacing on each side)
self.layer_widths = [self.track_width - self.horiz_layer_spacing, 1, self.track_width - self.vert_layer_spacing] self.layer_widths = [self.track_width - self.horiz_layer_spacing, 1, self.track_width - self.vert_layer_spacing]
def get_zindex(self,layer_num): def get_zindex(self,layer_num):
if layer_num==self.horiz_layer_number: if layer_num==self.horiz_layer_number:
return 0 return 0
@ -76,4 +84,24 @@ class router_tech:
return (min_width,min_spacing) return (min_width,min_spacing)
def get_supply_layer_width_space(self, zindex, widths=2):
"""
These are the width and spacing of a supply layer given a supply rail
of the given number of min wire widths.
"""
if zindex==1:
layer_name = self.vert_layer_name
elif zindex==0:
layer_name = self.horiz_layer_name
else:
debug.error("Invalid zindex for track", -1)
wire_width = widths*drc("minwidth_{0}".format(layer_name), 0, math.inf)
min_width = drc("minwidth_{0}".format(layer_name), wire_width, math.inf)
min_spacing = drc(str(layer_name)+"_to_"+str(layer_name), wire_width, math.inf)
return (min_width,min_spacing)

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@ -72,7 +72,7 @@ class supply_router(router):
#start_time = datetime.now() #start_time = datetime.now()
self.find_pins_and_blockages([self.vdd_name, self.gnd_name]) self.find_pins_and_blockages([self.vdd_name, self.gnd_name])
#print_time("Pins and blockages",datetime.now(), start_time) #print_time("Pins and blockages",datetime.now(), start_time)
#self.write_debug_gds("pin_enclosures.gds",stop_program=True) self.write_debug_gds("pin_enclosures.gds",stop_program=True)
# Add the supply rails in a mesh network and connect H/V with vias # Add the supply rails in a mesh network and connect H/V with vias
#start_time = datetime.now() #start_time = datetime.now()
@ -248,8 +248,8 @@ class supply_router(router):
rail_width = self.track_width*self.rail_track_width rail_width = self.track_width*self.rail_track_width
# Get the conservative width and spacing of the top rails # Get the conservative width and spacing of the top rails
(horizontal_width, horizontal_space) = self.get_layer_width_space(0, rail_width, rail_length) (horizontal_width, horizontal_space) = self.get_supply_layer_width_space(0,2)
(vertical_width, vertical_space) = self.get_layer_width_space(1, rail_width, rail_length) (vertical_width, vertical_space) = self.get_supply_layer_width_space(1,2)
width = max(horizontal_width, vertical_width) width = max(horizontal_width, vertical_width)
space = max(horizontal_space, vertical_space) space = max(horizontal_space, vertical_space)