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restore netlist on memchar

This commit is contained in:
Bugra Onal 2022-09-27 13:44:28 -07:00
parent 2d8d90952e
commit c6440dc16d
2 changed files with 8 additions and 40 deletions
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7
compiler/characterizer/delay.py
View File

@ -1130,15 +1130,17 @@ class delay(simulation):
Netlist reduced for simulation. Netlist reduced for simulation.
""" """
super().set_probe(probe_address, probe_data) super().set_probe(probe_address, probe_data)
self.prepare_netlist()
def prepare_netlist(self): def prepare_netlist(self):
""" Prepare a trimmed netlist and regular netlist. """ """ Prepare a trimmed netlist and regular netlist. """
# Set up to trim the netlist here if that is enabled # Set up to trim the netlist here if that is enabled
# TODO: Copy old netlist if memchar
if OPTS.trim_netlist: if OPTS.trim_netlist:
self.trim_sp_file = "{0}trimmed.sp".format(self.output_path) self.trim_sp_file = "{0}trimmed.sp".format(self.output_path)
self.sram.sp_write(self.trim_sp_file, lvs=False, trim=True) # Only genrate spice when running openram process
if OPTS.top_process == "openram":
self.sram.sp_write(self.trim_sp_file, lvs=False, trim=True)
else: else:
# The non-reduced netlist file when it is disabled # The non-reduced netlist file when it is disabled
self.trim_sp_file = "{0}sram.sp".format(self.output_path) self.trim_sp_file = "{0}sram.sp".format(self.output_path)
@ -1153,6 +1155,7 @@ class delay(simulation):
"""Sets values which are dependent on the data address/bit being tested.""" """Sets values which are dependent on the data address/bit being tested."""
self.set_probe(probe_address, probe_data) self.set_probe(probe_address, probe_data)
self.prepare_netlist()
self.create_graph() self.create_graph()
self.set_internal_spice_names() self.set_internal_spice_names()
self.create_measurement_names() self.create_measurement_names()

41
compiler/characterizer/fake_sram.py
View File

@ -10,44 +10,9 @@ class fake_sram(sram_config):
""" """
def __init__(self, name, word_size, num_words, write_size=None, num_banks=1, def __init__(self, name, word_size, num_words, write_size=None, num_banks=1,
words_per_row=None, num_spare_rows=0, num_spare_cols=0): words_per_row=None, num_spare_rows=0, num_spare_cols=0):
self.name = name sram_config.__init__(self, name, word_size, num_words, write_size=None,
self.word_size = word_size num_banks=1, words_per_row=None, num_spare_rows=0,
self.num_words = num_words num_spare_cols=0)
# Don't add a write mask if it is the same size as the data word
if write_size and write_size==word_size:
self.write_size = None
else:
self.write_size = write_size
self.num_banks = num_banks
self.num_spare_rows = num_spare_rows
self.num_spare_cols = num_spare_cols
try:
from tech import array_row_multiple
self.array_row_multiple = array_row_multiple
except ImportError:
self.array_row_multiple = 1
try:
from tech import array_col_multiple
self.array_col_multiple = array_col_multiple
except ImportError:
self.array_col_multiple = 1
if self.write_size:
self.num_wmasks = int(ceil(self.word_size / self.write_size))
else:
self.num_wmasks = 0
if not self.num_spare_cols:
self.num_spare_cols = 0
if not self.num_spare_rows:
self.num_spare_rows = 0
# This will get over-written when we determine the organization
self.words_per_row = words_per_row
self.compute_sizes()
def setup_multiport_constants(self): def setup_multiport_constants(self):
""" """