mirror of https://github.com/VLSIDA/OpenRAM.git
Rotate via and PEP8 formatting
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23501c7b35
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@ -115,7 +115,7 @@ class wordline_driver(design.design):
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"vdd", "gnd"])
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"vdd", "gnd"])
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def place_drivers(self):
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def place_drivers(self):
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nand2_xoffset = 2*self.m1_width + 5*self.m1_space
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nand2_xoffset = 2 * self.m1_width + 5 * self.m1_space
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inv2_xoffset = nand2_xoffset + self.nand2.width
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inv2_xoffset = nand2_xoffset + self.nand2.width
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self.width = inv2_xoffset + self.inv.width
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self.width = inv2_xoffset + self.inv.width
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@ -123,10 +123,10 @@ class wordline_driver(design.design):
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for row in range(self.rows):
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for row in range(self.rows):
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if (row % 2):
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if (row % 2):
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y_offset = self.inv.height*(row + 1)
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y_offset = self.inv.height * (row + 1)
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inst_mirror = "MX"
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inst_mirror = "MX"
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else:
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else:
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y_offset = self.inv.height*row
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y_offset = self.inv.height * row
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inst_mirror = "R0"
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inst_mirror = "R0"
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nand2_offset = [nand2_xoffset, y_offset]
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nand2_offset = [nand2_xoffset, y_offset]
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@ -168,8 +168,8 @@ class wordline_driver(design.design):
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zr_pos = nand_inst.get_pin("Z").rc()
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zr_pos = nand_inst.get_pin("Z").rc()
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al_pos = inv2_inst.get_pin("A").lc()
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al_pos = inv2_inst.get_pin("A").lc()
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# ensure the bend is in the middle
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# ensure the bend is in the middle
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mid1_pos = vector(0.5*(zr_pos.x+al_pos.x), zr_pos.y)
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mid1_pos = vector(0.5 * (zr_pos.x + al_pos.x), zr_pos.y)
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mid2_pos = vector(0.5*(zr_pos.x+al_pos.x), al_pos.y)
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mid2_pos = vector(0.5 * (zr_pos.x + al_pos.x), al_pos.y)
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self.add_path("m1", [zr_pos, mid1_pos, mid2_pos, al_pos])
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self.add_path("m1", [zr_pos, mid1_pos, mid2_pos, al_pos])
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# connect the decoder input pin to nand2 B
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# connect the decoder input pin to nand2 B
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@ -234,8 +234,8 @@ class pnand2(pgate.pgate):
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self.add_layout_pin_rect_center(text="Z",
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self.add_layout_pin_rect_center(text="Z",
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layer="m1",
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layer="m1",
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offset=out_offset,
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offset=out_offset,
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width=contact.m1_via.first_layer_height,
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width=contact.m1_via.first_layer_width,
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height=contact.m1_via.first_layer_width)
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height=contact.m1_via.first_layer_height)
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def analytical_power(self, corner, load):
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def analytical_power(self, corner, load):
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"""Returns dynamic and leakage power. Results in nW"""
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"""Returns dynamic and leakage power. Results in nW"""
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@ -259,7 +259,7 @@ class pnand3(pgate.pgate):
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# In fF
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# In fF
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c_para = spice["min_tx_drain_c"] * (self.nmos_size / parameter["min_tx_size"])
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c_para = spice["min_tx_drain_c"] * (self.nmos_size / parameter["min_tx_size"])
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transition_prob = 0.1094
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transition_prob = 0.1094
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return transition_prob *(c_load + c_para)
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return transition_prob * (c_load + c_para)
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def input_load(self):
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def input_load(self):
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"""Return the relative input capacitance of a single input"""
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"""Return the relative input capacitance of a single input"""
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