mirror of https://github.com/VLSIDA/OpenRAM.git
Remove old commented code
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@ -93,12 +93,6 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa
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f.write('puts "Finished reading gds {}"\n'.format(gds_name))
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f.write('puts "Finished reading gds {}"\n'.format(gds_name))
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f.write("load {}\n".format(cell_name))
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f.write("load {}\n".format(cell_name))
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f.write('puts "Finished loading cell {}"\n'.format(cell_name))
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f.write('puts "Finished loading cell {}"\n'.format(cell_name))
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# Flatten the cell to get rid of DRCs spanning multiple layers
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# (e.g. with routes)
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# f.write("flatten {}_new\n".format(cell_name))
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# f.write("load {}_new\n".format(cell_name))
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# f.write("cellname rename {0}_new {0}\n".format(cell_name))
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# f.write("load {}\n".format(cell_name))
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f.write("cellname delete \\(UNNAMED\\)\n")
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f.write("cellname delete \\(UNNAMED\\)\n")
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f.write("writeall force\n")
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f.write("writeall force\n")
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f.write("select top cell\n")
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f.write("select top cell\n")
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