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OpenRAM
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Channel route dout wires as well in read write ports

This commit is contained in:
mrg 2020-07-01 14:44:01 -07:00
parent bb18d05f75
commit c340870ba0
3 changed files with 50 additions and 22 deletions
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2
compiler/base/channel_route.py
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@ -161,7 +161,7 @@ class channel_route(design.design):
else: else:
# FIXME: We don't support cyclic VCGs right now. # FIXME: We don't support cyclic VCGs right now.
debug.error("Cyclic VCG in channel router.", -1) debug.error("Cyclic VCG in channel router.", -1)
# These are the pins we'll have to connect # These are the pins we'll have to connect
pin_list = nets[net_name] pin_list = nets[net_name]
# print("Routing:", net_name, [x.name for x in pin_list]) # print("Routing:", net_name, [x.name for x in pin_list])

6
compiler/base/hierarchy_layout.py
View File

@ -1176,9 +1176,9 @@ class layout():
self.add_path(layer, self.add_path(layer,
[pin_loc, peri_pin_loc]) [pin_loc, peri_pin_loc])
self.add_layout_pin_rect_center(text=name, return self.add_layout_pin_rect_center(text=name,
layer=layer, layer=layer,
offset=peri_pin_loc) offset=peri_pin_loc)
def add_power_ring(self, bbox): def add_power_ring(self, bbox):
""" """

64
compiler/sram/sram_1bank.py
View File

@ -81,6 +81,10 @@ class sram_1bank(sram_base):
# Write ports need the data input flops and write mask flops # Write ports need the data input flops and write mask flops
if port in self.write_ports: if port in self.write_ports:
self.data_bus_size[port] += self.num_wmasks + self.word_size self.data_bus_size[port] += self.num_wmasks + self.word_size
# This is for the din pins that get routed in the same channel
# when we have dout and din together
if port in self.readwrite_ports:
self.data_bus_size[port] += self.word_size
# Convert to length # Convert to length
self.data_bus_size[port] *= self.m4_nonpref_pitch self.data_bus_size[port] *= self.m4_nonpref_pitch
# Add the gap in unit length # Add the gap in unit length
@ -237,18 +241,45 @@ class sram_1bank(sram_base):
"clk", "clk",
"clk{}".format(port)) "clk{}".format(port))
# Data output pins go to BOTTOM/TOP # Data input pins go to BOTTOM/TOP
if port in self.read_ports: din_ports = []
if port in self.write_ports:
for bit in range(self.word_size + self.num_spare_cols): for bit in range(self.word_size + self.num_spare_cols):
if OPTS.perimeter_pins: if OPTS.perimeter_pins:
p = self.add_perimeter_pin(name="din{0}[{1}]".format(port, bit),
pin=self.data_dff_insts[port].get_pin("din_{0}".format(bit)),
side=bottom_or_top,
bbox=bbox)
din_ports.append(p)
else:
self.copy_layout_pin(self.bank_inst,
"din{0}_{1}".format(port, bit),
"din{0}[{1}]".format(port, bit))
# Data output pins go to BOTTOM/TOP
if port in self.readwrite_ports and OPTS.perimeter_pins:
for bit in range(self.word_size + self.num_spare_cols):
# This should be routed next to the din pin
p = din_ports[bit]
self.add_layout_pin_rect_center(text="dout{0}[{1}]".format(port, bit),
layer=p.layer,
offset=p.center() + vector(self.m3_pitch, 0),
width=p.width(),
height=p.height())
elif port in self.read_ports:
for bit in range(self.word_size + self.num_spare_cols):
if OPTS.perimeter_pins:
# This should have a clear route to the perimeter if there are no din routes
self.add_perimeter_pin(name="dout{0}[{1}]".format(port, bit), self.add_perimeter_pin(name="dout{0}[{1}]".format(port, bit),
pin=self.bank_inst.get_pin("dout{0}_{1}".format(port, bit)), pin=self.bank_inst.get_pin("dout{0}_{1}".format(port, bit)),
side=bottom_or_top, side=bottom_or_top,
bbox=bbox) bbox=bbox)
else: else:
self.copy_layout_pin(self.bank_inst, self.copy_layout_pin(self.data_dff_insts[port],
"dout{0}_{1}".format(port, bit), "dout_{}".format(bit),
"dout{0}[{1}]".format(port, bit)) "dout{0}[{1}]".format(port, bit))
# Lower address bits go to BOTTOM/TOP # Lower address bits go to BOTTOM/TOP
for bit in range(self.col_addr_size): for bit in range(self.col_addr_size):
@ -274,19 +305,6 @@ class sram_1bank(sram_base):
"din_{}".format(bit), "din_{}".format(bit),
"addr{0}[{1}]".format(port, bit + self.col_addr_size)) "addr{0}[{1}]".format(port, bit + self.col_addr_size))
# Data input pins go to BOTTOM/TOP
if port in self.write_ports:
for bit in range(self.word_size + self.num_spare_cols):
if OPTS.perimeter_pins:
self.add_perimeter_pin(name="din{0}[{1}]".format(port, bit),
pin=self.data_dff_insts[port].get_pin("din_{}".format(bit)),
side=bottom_or_top,
bbox=bbox)
else:
self.copy_layout_pin(self.data_dff_insts[port],
"din_{}".format(bit),
"din{0}[{1}]".format(port, bit))
# Write mask pins go to BOTTOM/TOP # Write mask pins go to BOTTOM/TOP
if port in self.write_ports: if port in self.write_ports:
if self.write_size: if self.write_size:
@ -349,12 +367,22 @@ class sram_1bank(sram_base):
route_map.extend(list(zip(bank_pins, dff_pins))) route_map.extend(list(zip(bank_pins, dff_pins)))
if port in self.write_ports: if port in self.write_ports:
# data dff # synchronized inputs from data dff
dff_names = ["dout_{}".format(x) for x in range(self.word_size + self.num_spare_cols)] dff_names = ["dout_{}".format(x) for x in range(self.word_size + self.num_spare_cols)]
dff_pins = [self.data_dff_insts[port].get_pin(x) for x in dff_names] dff_pins = [self.data_dff_insts[port].get_pin(x) for x in dff_names]
bank_names = ["din{0}_{1}".format(port, x) for x in range(self.word_size + self.num_spare_cols)] bank_names = ["din{0}_{1}".format(port, x) for x in range(self.word_size + self.num_spare_cols)]
bank_pins = [self.bank_inst.get_pin(x) for x in bank_names] bank_pins = [self.bank_inst.get_pin(x) for x in bank_names]
route_map.extend(list(zip(bank_pins, dff_pins))) route_map.extend(list(zip(bank_pins, dff_pins)))
if port in self.readwrite_ports and OPTS.perimeter_pins:
# outputs from sense amp
# These are the output pins which had their pin placed on the perimeter, so route from the
# sense amp which should not align with write driver input
sram_names = ["dout{0}[{1}]".format(port, x) for x in range(self.word_size + self.num_spare_cols)]
sram_pins = [self.get_pin(x) for x in sram_names]
bank_names = ["dout{0}_{1}".format(port, x) for x in range(self.word_size + self.num_spare_cols)]
bank_pins = [self.bank_inst.get_pin(x) for x in bank_names]
route_map.extend(list(zip(bank_pins, sram_pins)))
if self.num_wmasks > 0 and port in self.write_ports: if self.num_wmasks > 0 and port in self.write_ports:
layer_stack = self.m3_stack layer_stack = self.m3_stack