luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix ngspice results

This commit is contained in:
Matt Guthaus 2016-11-15 09:41:30 -08:00
parent eb57c6e7fd
commit c33e283283
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
compiler/tests/21_ngspice_delay_test.py
View File

@ -51,10 +51,10 @@ class timing_sram_test(unittest.TestCase):
data = d.analyze(probe_address, probe_data) data = d.analyze(probe_address, probe_data)
if OPTS.tech_name == "freepdk45": if OPTS.tech_name == "freepdk45":
self.assertTrue(isclose(data['delay1'],0.01333683)) # diff than hspice self.assertTrue(isclose(data['delay1'],0.013649)) # diff than hspice
self.assertTrue(isclose(data['delay0'],0.23396480000000003)) # diff than hspice self.assertTrue(isclose(data['delay0'],0.22893)) # diff than hspice
self.assertTrue(isclose(data['min_period1'],0.079193115234375)) # diff than hspice self.assertTrue(isclose(data['min_period1'],0.078582763671875)) # diff than hspice
self.assertTrue(isclose(data['min_period0'],0.260162353515625)) # diff than hspice self.assertTrue(isclose(data['min_period0'],0.25543212890625)) # diff than hspice
elif OPTS.tech_name == "scn3me_subm": elif OPTS.tech_name == "scn3me_subm":
self.assertTrue(isclose(data['delay1'],1.617351)) # diff than hspice self.assertTrue(isclose(data['delay1'],1.617351)) # diff than hspice
self.assertTrue(isclose(data['delay0'],0.2980481)) # diff than hspice self.assertTrue(isclose(data['delay0'],0.2980481)) # diff than hspice