mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-02 02:57:53 +02:00
Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
This commit is contained in:
Michael Timothy Grimes
@@ -21,7 +21,7 @@ class pinvbuf_test(openram_test):
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import pinvbuf
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debug.info(2, "Testing inverter/buffer 4x 8x")
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a = pinvbuf.pinvbuf(4,8)
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a = pinvbuf.pinvbuf(8)
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self.local_check(a)
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globals.end_openram()
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@@ -41,7 +41,7 @@ class timing_sram_test(openram_test):
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probe_address = "1" * s.s.addr_size
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probe_data = s.s.word_size - 1
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debug.info(1, "Probe address {0} probe data {1}".format(probe_address, probe_data))
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debug.info(1, "Probe address {0} probe data bit {1}".format(probe_address, probe_data))
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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d = delay(s.s, tempspice, corner)
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@@ -49,41 +49,36 @@ class timing_sram_test(openram_test):
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loads = [tech.spice["msflop_in_cap"]*4]
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slews = [tech.spice["rise_time"]*2]
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data = d.analyze(probe_address, probe_data, slews, loads)
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#print data
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if OPTS.tech_name == "freepdk45":
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golden_data = {'leakage_power': 0.0006964536000000001,
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'delay_lh': [0.0573055],
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'read0_power': [0.0337812],
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'read1_power': [0.032946500000000004],
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'write1_power': [0.0361529],
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'write0_power': [0.026179099999999997],
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'slew_hl': [0.0285185],
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'min_period': 0.205,
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'delay_hl': [0.070554],
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'slew_lh': [0.0190073]}
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golden_data = {'delay_hl': [2.5614],
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'delay_lh': [0.22929839999999999],
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'leakage_power': 0.0020326,
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'min_period': 4.844,
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'read0_power': [0.0497676],
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'read1_power': [0.0463576],
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'slew_hl': [0.1119293],
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'slew_lh': [0.0237043],
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'write0_power': [0.0494321],
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'write1_power': [0.0457268]}
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elif OPTS.tech_name == "scn3me_subm":
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golden_data = {'leakage_power': 0.0004004581,
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'delay_lh': [0.6538954],
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'read0_power': [9.7622],
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'read1_power': [9.589],
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'write1_power': [10.8],
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'write0_power': [6.928400000000001],
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'slew_hl': [0.8321625],
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'min_period': 2.344,
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'delay_hl': [0.9019090999999999],
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'slew_lh': [0.5896232]}
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golden_data = {'delay_hl': [6.0052],
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'delay_lh': [2.2886],
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'leakage_power': 0.025629199999999998,
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'min_period': 9.375,
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'read0_power': [8.8721],
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'read1_power': [8.3179],
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'slew_hl': [1.0746],
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'slew_lh': [0.413426],
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'write0_power': [8.6601],
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'write1_power': [8.0397]}
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else:
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self.assertTrue(False) # other techs fail
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# Check if no too many or too few results
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self.assertTrue(len(data.keys())==len(golden_data.keys()))
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# Check each result
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for k in data.keys():
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if type(data[k])==list:
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for i in range(len(data[k])):
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self.isclose(data[k][i],golden_data[k][i],0.15)
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else:
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self.isclose(data[k],golden_data[k],0.15)
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self.assertTrue(self.check_golden_data(data,golden_data,0.25))
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globals.end_openram()
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# instantiate a copdsay of the class to actually run the test
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@@ -49,13 +49,8 @@ class timing_setup_test(openram_test):
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# Check if no too many or too few results
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self.assertTrue(len(data.keys())==len(golden_data.keys()))
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# Check each result
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for k in data.keys():
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if type(data[k])==list:
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for i in range(len(data[k])):
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self.isclose(data[k][i],golden_data[k][i],0.15)
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else:
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self.isclose(data[k],golden_data[k],0.15)
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self.assertTrue(self.check_golden_data(data,golden_data,0.25))
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globals.end_openram()
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@@ -17,6 +17,7 @@ class timing_sram_test(openram_test):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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OPTS.spice_name="ngspice"
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OPTS.analytical_delay = False
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OPTS.trim_netlist = False
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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@@ -39,7 +40,7 @@ class timing_sram_test(openram_test):
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probe_address = "1" * s.s.addr_size
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probe_data = s.s.word_size - 1
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debug.info(1, "Probe address {0} probe data {1}".format(probe_address, probe_data))
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debug.info(1, "Probe address {0} probe data bit {1}".format(probe_address, probe_data))
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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d = delay(s.s, tempspice, corner)
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@@ -47,41 +48,36 @@ class timing_sram_test(openram_test):
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loads = [tech.spice["msflop_in_cap"]*4]
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slews = [tech.spice["rise_time"]*2]
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data = d.analyze(probe_address, probe_data, slews, loads)
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#print data
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if OPTS.tech_name == "freepdk45":
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golden_data = {'leakage_power': 0.0007348262,
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'delay_lh': [0.05799613],
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'read0_power': [0.0384102],
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'read1_power': [0.03279848],
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'write1_power': [0.03693655],
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'write0_power': [0.02717752],
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'slew_hl': [0.03607912],
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'min_period': 0.742,
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'delay_hl': [0.3929995],
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'slew_lh': [0.02160862]}
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golden_data = {'delay_hl': [2.562671],
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'delay_lh': [0.2320771],
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'leakage_power': 0.00102373,
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'min_period': 4.844,
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'read0_power': [0.047404110000000006],
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'read1_power': [0.0438884],
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'slew_hl': [0.1140206],
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'slew_lh': [0.02492785],
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'write0_power': [0.04765188],
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'write1_power': [0.04434999]}
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elif OPTS.tech_name == "scn3me_subm":
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golden_data = {'leakage_power': 0.00142014,
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'delay_lh': [0.8018421],
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'read0_power': [11.44908],
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'read1_power': [11.416549999999999],
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'write1_power': [11.718020000000001],
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'write0_power': [8.250219],
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'slew_hl': [0.8273725],
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'min_period': 34,
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'delay_hl': [1.085861],
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'slew_lh': [0.5730144]}
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golden_data = {'delay_hl': [11.69536],
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'delay_lh': [1.260921],
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'leakage_power': 0.00039469710000000004,
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'min_period': 20.0,
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'read0_power': [4.40238],
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'read1_power': [4.126633],
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'slew_hl': [1.259555],
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'slew_lh': [0.9150649],
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'write0_power': [4.988347],
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'write1_power': [4.473887]}
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else:
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self.assertTrue(False) # other techs fail
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# Check if no too many or too few results
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self.assertTrue(len(data.keys())==len(golden_data.keys()))
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# Check each result
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for k in data.keys():
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if type(data[k])==list:
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for i in range(len(data[k])):
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self.isclose(data[k][i],golden_data[k][i],0.15)
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else:
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self.isclose(data[k],golden_data[k],0.15)
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self.assertTrue(self.check_golden_data(data,golden_data,0.25))
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globals.end_openram()
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@@ -49,14 +49,9 @@ class timing_setup_test(openram_test):
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# Check if no too many or too few results
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self.assertTrue(len(data.keys())==len(golden_data.keys()))
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# Check each result
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for k in data.keys():
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if type(data[k])==list:
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for i in range(len(data[k])):
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self.isclose(data[k][i],golden_data[k][i],0.15)
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else:
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self.isclose(data[k],golden_data[k],0.15)
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self.assertTrue(self.check_golden_data(data,golden_data,0.25))
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reload(characterizer)
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globals.end_openram()
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@@ -40,7 +40,7 @@ class lib_test(openram_test):
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newname = filename.replace(".lib","_analytical.lib")
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libname = "{0}/{1}".format(OPTS.openram_temp,filename)
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golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),newname)
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self.isapproxdiff(libname,golden,0.15)
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self.assertTrue(self.isapproxdiff(libname,golden,0.15))
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globals.end_openram()
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@@ -49,7 +49,7 @@ class lib_test(openram_test):
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newname = filename.replace(".lib","_pruned.lib")
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libname = "{0}/{1}".format(OPTS.openram_temp,filename)
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golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),newname)
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self.isapproxdiff(libname,golden,0.40)
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self.assertTrue(self.isapproxdiff(libname,golden,0.40))
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reload(characterizer)
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globals.end_openram()
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@@ -48,7 +48,7 @@ class lib_test(openram_test):
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for filename in lib_files:
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libname = "{0}/{1}".format(OPTS.openram_temp,filename)
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golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),filename)
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self.isapproxdiff(libname,golden,0.40)
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self.assertTrue(self.isapproxdiff(libname,golden,0.40))
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reload(characterizer)
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globals.end_openram()
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@@ -64,10 +64,13 @@ class openram_test(openram_test):
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self.assertTrue(len(files)>0)
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# grep any errors from the output
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output = open("{0}/output.log".format(out_path),"r").read()
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output_log = open("{0}/output.log".format(out_path),"r")
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output = output_log.read()
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output_log.close()
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self.assertEqual(len(re.findall('ERROR',output)),0)
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self.assertEqual(len(re.findall('WARNING',output)),0)
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# now clean up the directory
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if os.path.exists(out_path):
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shutil.rmtree(out_path, ignore_errors=True)
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@@ -78,27 +78,31 @@ cell (sram_2_16_1_freepdk45){
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dont_use : true;
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map_only : true;
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dont_touch : true;
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area : 1032.3999375;
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area : 948.52275;
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leakage_power () {
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when : "CSb";
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value : 0.0008128352;
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value : 0.0021292;
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}
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cell_leakage_power : 0;
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bus(DATA){
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bus(DIN){
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bus_type : DATA;
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direction : inout;
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direction : in;
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max_capacitance : 1.6728;
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min_capacitance : 0.052275;
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three_state : "!OEb & !clk";
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memory_write(){
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address : ADDR;
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clocked_on : clk;
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}
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bus(DOUT){
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bus_type : DATA;
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direction : out;
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max_capacitance : 1.6728;
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min_capacitance : 0.052275;
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memory_read(){
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address : ADDR;
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}
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pin(DATA[1:0]){
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pin(DOUT[1:0]){
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timing(){
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timing_type : setup_rising;
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related_pin : "clk";
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@@ -130,26 +134,26 @@ cell (sram_2_16_1_freepdk45){
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timing(){
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timing_sense : non_unate;
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related_pin : "clk";
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timing_type : falling_edge;
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timing_type : rising_edge;
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cell_rise(CELL_TABLE) {
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values("0.055, 0.056, 0.063",\
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"0.056, 0.057, 0.063",\
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"0.061, 0.062, 0.069");
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values("0.229, 0.23, 0.234",\
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"0.23, 0.23, 0.234",\
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"0.236, 0.236, 0.24");
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}
|
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cell_fall(CELL_TABLE) {
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values("0.067, 0.068, 0.076",\
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"0.067, 0.068, 0.077",\
|
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"0.073, 0.074, 0.082");
|
||||
values("2.555, 2.556, 2.568",\
|
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"2.555, 2.557, 2.569",\
|
||||
"2.562, 2.563, 2.575");
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}
|
||||
rise_transition(CELL_TABLE) {
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values("0.013, 0.015, 0.026",\
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"0.013, 0.015, 0.026",\
|
||||
"0.014, 0.015, 0.026");
|
||||
values("0.02, 0.021, 0.028",\
|
||||
"0.02, 0.021, 0.028",\
|
||||
"0.02, 0.021, 0.028");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.023, 0.024, 0.037",\
|
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"0.023, 0.024, 0.037",\
|
||||
"0.024, 0.024, 0.037");
|
||||
values("0.111, 0.112, 0.115",\
|
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"0.111, 0.111, 0.115",\
|
||||
"0.111, 0.111, 0.116");
|
||||
}
|
||||
}
|
||||
}
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@@ -298,19 +302,19 @@ cell (sram_2_16_1_freepdk45){
|
||||
internal_power(){
|
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when : "!CSb & clk & !WEb";
|
||||
rise_power(scalar){
|
||||
values("0.0175059861111");
|
||||
values("0.027431397222222223");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.0175059861111");
|
||||
values("0.027431397222222223");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb & !clk & WEb";
|
||||
rise_power(scalar){
|
||||
values("0.0218644166667");
|
||||
values("0.026240397222222222");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.0218644166667");
|
||||
values("0.026240397222222222");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
@@ -326,20 +330,20 @@ cell (sram_2_16_1_freepdk45){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk;
|
||||
rise_constraint(scalar) {
|
||||
values("0.117");
|
||||
values("2.422");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.117");
|
||||
values("2.422");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk;
|
||||
rise_constraint(scalar) {
|
||||
values("0.234");
|
||||
values("4.844");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.234");
|
||||
values("4.844");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -78,27 +78,31 @@ cell (sram_2_16_1_freepdk45){
|
||||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 1032.3999375;
|
||||
area : 948.52275;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb";
|
||||
value : 0.000173;
|
||||
value : 0.000168;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
bus(DATA){
|
||||
bus(DIN){
|
||||
bus_type : DATA;
|
||||
direction : inout;
|
||||
direction : in;
|
||||
max_capacitance : 1.6728;
|
||||
min_capacitance : 0.052275;
|
||||
three_state : "!OEb & !clk";
|
||||
memory_write(){
|
||||
address : ADDR;
|
||||
clocked_on : clk;
|
||||
}
|
||||
bus(DOUT){
|
||||
bus_type : DATA;
|
||||
direction : out;
|
||||
max_capacitance : 1.6728;
|
||||
min_capacitance : 0.052275;
|
||||
memory_read(){
|
||||
address : ADDR;
|
||||
}
|
||||
pin(DATA[1:0]){
|
||||
pin(DOUT[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
@@ -130,16 +134,16 @@ cell (sram_2_16_1_freepdk45){
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk";
|
||||
timing_type : falling_edge;
|
||||
timing_type : rising_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.123, 0.124, 0.133",\
|
||||
"0.123, 0.124, 0.133",\
|
||||
"0.123, 0.124, 0.133");
|
||||
values("0.103, 0.104, 0.113",\
|
||||
"0.103, 0.104, 0.113",\
|
||||
"0.103, 0.104, 0.113");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("0.123, 0.124, 0.133",\
|
||||
"0.123, 0.124, 0.133",\
|
||||
"0.123, 0.124, 0.133");
|
||||
values("0.103, 0.104, 0.113",\
|
||||
"0.103, 0.104, 0.113",\
|
||||
"0.103, 0.104, 0.113");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.006, 0.007, 0.018",\
|
||||
@@ -298,19 +302,19 @@ cell (sram_2_16_1_freepdk45){
|
||||
internal_power(){
|
||||
when : "!CSb & clk & !WEb";
|
||||
rise_power(scalar){
|
||||
values("0.065526962224");
|
||||
values("0.0739870044551111");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.065526962224");
|
||||
values("0.0739870044551111");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb & !clk & WEb";
|
||||
rise_power(scalar){
|
||||
values("0.065526962224");
|
||||
values("0.0739870044551111");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.065526962224");
|
||||
values("0.0739870044551111");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
@@ -336,10 +340,10 @@ cell (sram_2_16_1_freepdk45){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk;
|
||||
rise_constraint(scalar) {
|
||||
values("0.0");
|
||||
values("0");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.0");
|
||||
values("0");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -78,27 +78,31 @@ cell (sram_2_16_1_freepdk45){
|
||||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 1032.3999375;
|
||||
area : 948.52275;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb";
|
||||
value : 0.0008128352;
|
||||
value : 0.0021292;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
bus(DATA){
|
||||
bus(DIN){
|
||||
bus_type : DATA;
|
||||
direction : inout;
|
||||
direction : in;
|
||||
max_capacitance : 1.6728;
|
||||
min_capacitance : 0.052275;
|
||||
three_state : "!OEb & !clk";
|
||||
memory_write(){
|
||||
address : ADDR;
|
||||
clocked_on : clk;
|
||||
}
|
||||
bus(DOUT){
|
||||
bus_type : DATA;
|
||||
direction : out;
|
||||
max_capacitance : 1.6728;
|
||||
min_capacitance : 0.052275;
|
||||
memory_read(){
|
||||
address : ADDR;
|
||||
}
|
||||
pin(DATA[1:0]){
|
||||
pin(DOUT[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
@@ -130,26 +134,26 @@ cell (sram_2_16_1_freepdk45){
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk";
|
||||
timing_type : falling_edge;
|
||||
timing_type : rising_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.054, 0.055, 0.061",\
|
||||
"0.055, 0.056, 0.062",\
|
||||
"0.06, 0.061, 0.068");
|
||||
values("0.227, 0.227, 0.231",\
|
||||
"0.227, 0.228, 0.232",\
|
||||
"0.233, 0.234, 0.238");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("0.066, 0.067, 0.075",\
|
||||
"0.067, 0.068, 0.076",\
|
||||
"0.072, 0.073, 0.082");
|
||||
values("2.555, 2.557, 2.569",\
|
||||
"2.556, 2.557, 2.569",\
|
||||
"2.562, 2.563, 2.576");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.013, 0.014, 0.026",\
|
||||
"0.013, 0.015, 0.026",\
|
||||
"0.013, 0.015, 0.026");
|
||||
values("0.02, 0.021, 0.028",\
|
||||
"0.02, 0.021, 0.028",\
|
||||
"0.02, 0.021, 0.028");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.023, 0.024, 0.037",\
|
||||
"0.023, 0.024, 0.037",\
|
||||
"0.024, 0.024, 0.037");
|
||||
values("0.11, 0.11, 0.114",\
|
||||
"0.109, 0.11, 0.113",\
|
||||
"0.11, 0.11, 0.114");
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -298,19 +302,19 @@ cell (sram_2_16_1_freepdk45){
|
||||
internal_power(){
|
||||
when : "!CSb & clk & !WEb";
|
||||
rise_power(scalar){
|
||||
values("0.0159801855389");
|
||||
values("0.025181683333333333");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.0159801855389");
|
||||
values("0.025181683333333333");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb & !clk & WEb";
|
||||
rise_power(scalar){
|
||||
values("0.0171325605389");
|
||||
values("0.024945991666666667");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.0171325605389");
|
||||
values("0.024945991666666667");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
@@ -326,20 +330,20 @@ cell (sram_2_16_1_freepdk45){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk;
|
||||
rise_constraint(scalar) {
|
||||
values("0.1125");
|
||||
values("2.422");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.1125");
|
||||
values("2.422");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk;
|
||||
rise_constraint(scalar) {
|
||||
values("0.225");
|
||||
values("4.844");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.225");
|
||||
values("4.844");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -78,27 +78,31 @@ cell (sram_2_16_1_scn3me_subm){
|
||||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 134589.78;
|
||||
area : 142800.38999999998;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb";
|
||||
value : 0.0004764706;
|
||||
value : 0.0252988;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
bus(DATA){
|
||||
bus(DIN){
|
||||
bus_type : DATA;
|
||||
direction : inout;
|
||||
direction : in;
|
||||
max_capacitance : 78.5936;
|
||||
min_capacitance : 2.45605;
|
||||
three_state : "!OEb & !clk";
|
||||
memory_write(){
|
||||
address : ADDR;
|
||||
clocked_on : clk;
|
||||
}
|
||||
bus(DOUT){
|
||||
bus_type : DATA;
|
||||
direction : out;
|
||||
max_capacitance : 78.5936;
|
||||
min_capacitance : 2.45605;
|
||||
memory_read(){
|
||||
address : ADDR;
|
||||
}
|
||||
pin(DATA[1:0]){
|
||||
pin(DOUT[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
@@ -130,26 +134,26 @@ cell (sram_2_16_1_scn3me_subm){
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk";
|
||||
timing_type : falling_edge;
|
||||
timing_type : rising_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.474, 0.52, 0.888",\
|
||||
"0.477, 0.522, 0.892",\
|
||||
"0.517, 0.561, 0.929");
|
||||
values("0.945, 0.976, 1.139",\
|
||||
"0.948, 0.98, 1.143",\
|
||||
"1.003, 1.036, 1.202");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("0.582, 0.658, 1.26",\
|
||||
"0.586, 0.661, 1.262",\
|
||||
"0.626, 0.7, 1.298");
|
||||
values("11.211, 11.266, 11.754",\
|
||||
"11.212, 11.267, 11.755",\
|
||||
"11.264, 11.319, 11.806");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.155, 0.233, 1.087",\
|
||||
"0.156, 0.235, 1.086",\
|
||||
"0.16, 0.239, 1.086");
|
||||
values("0.605, 0.629, 0.98",\
|
||||
"0.605, 0.629, 0.979",\
|
||||
"0.604, 0.628, 0.973");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.277, 0.356, 1.502",\
|
||||
"0.278, 0.358, 1.501",\
|
||||
"0.279, 0.363, 1.5");
|
||||
values("11.17, 11.175, 1.284",\
|
||||
"11.167, 11.173, 1.284",\
|
||||
"11.173, 11.179, 11.473");
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -298,19 +302,19 @@ cell (sram_2_16_1_scn3me_subm){
|
||||
internal_power(){
|
||||
when : "!CSb & clk & !WEb";
|
||||
rise_power(scalar){
|
||||
values("4.92665");
|
||||
values("2.1762222222222225");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("4.92665");
|
||||
values("2.1762222222222225");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb & !clk & WEb";
|
||||
rise_power(scalar){
|
||||
values("5.74515833333");
|
||||
values("2.167955555555556");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("5.74515833333");
|
||||
values("2.167955555555556");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
@@ -326,20 +330,20 @@ cell (sram_2_16_1_scn3me_subm){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk;
|
||||
rise_constraint(scalar) {
|
||||
values("1.875");
|
||||
values("9.6875");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("1.875");
|
||||
values("9.6875");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk;
|
||||
rise_constraint(scalar) {
|
||||
values("3.75");
|
||||
values("19.375");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("3.75");
|
||||
values("19.375");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -78,27 +78,31 @@ cell (sram_2_16_1_scn3me_subm){
|
||||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 134589.78;
|
||||
area : 142800.38999999998;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb";
|
||||
value : 0.000173;
|
||||
value : 0.000168;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
bus(DATA){
|
||||
bus(DIN){
|
||||
bus_type : DATA;
|
||||
direction : inout;
|
||||
direction : in;
|
||||
max_capacitance : 78.5936;
|
||||
min_capacitance : 2.45605;
|
||||
three_state : "!OEb & !clk";
|
||||
memory_write(){
|
||||
address : ADDR;
|
||||
clocked_on : clk;
|
||||
}
|
||||
bus(DOUT){
|
||||
bus_type : DATA;
|
||||
direction : out;
|
||||
max_capacitance : 78.5936;
|
||||
min_capacitance : 2.45605;
|
||||
memory_read(){
|
||||
address : ADDR;
|
||||
}
|
||||
pin(DATA[1:0]){
|
||||
pin(DOUT[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
@@ -130,16 +134,16 @@ cell (sram_2_16_1_scn3me_subm){
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk";
|
||||
timing_type : falling_edge;
|
||||
timing_type : rising_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.556, 0.603, 1.044",\
|
||||
"0.556, 0.603, 1.044",\
|
||||
"0.556, 0.603, 1.044");
|
||||
values("0.54, 0.587, 1.028",\
|
||||
"0.54, 0.587, 1.028",\
|
||||
"0.54, 0.587, 1.028");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("0.556, 0.603, 1.044",\
|
||||
"0.556, 0.603, 1.044",\
|
||||
"0.556, 0.603, 1.044");
|
||||
values("0.54, 0.587, 1.028",\
|
||||
"0.54, 0.587, 1.028",\
|
||||
"0.54, 0.587, 1.028");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.024, 0.081, 0.61",\
|
||||
@@ -298,19 +302,19 @@ cell (sram_2_16_1_scn3me_subm){
|
||||
internal_power(){
|
||||
when : "!CSb & clk & !WEb";
|
||||
rise_power(scalar){
|
||||
values("10.9314668117");
|
||||
values("10.559086132533329");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("10.9314668117");
|
||||
values("10.559086132533329");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb & !clk & WEb";
|
||||
rise_power(scalar){
|
||||
values("10.9314668117");
|
||||
values("10.559086132533329");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("10.9314668117");
|
||||
values("10.559086132533329");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
@@ -336,10 +340,10 @@ cell (sram_2_16_1_scn3me_subm){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk;
|
||||
rise_constraint(scalar) {
|
||||
values("0.0");
|
||||
values("0");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.0");
|
||||
values("0");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -78,27 +78,31 @@ cell (sram_2_16_1_scn3me_subm){
|
||||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 134589.78;
|
||||
area : 142800.38999999998;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb";
|
||||
value : 0.0004764706;
|
||||
value : 0.0252988;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
bus(DATA){
|
||||
bus(DIN){
|
||||
bus_type : DATA;
|
||||
direction : inout;
|
||||
direction : in;
|
||||
max_capacitance : 78.5936;
|
||||
min_capacitance : 2.45605;
|
||||
three_state : "!OEb & !clk";
|
||||
memory_write(){
|
||||
address : ADDR;
|
||||
clocked_on : clk;
|
||||
}
|
||||
bus(DOUT){
|
||||
bus_type : DATA;
|
||||
direction : out;
|
||||
max_capacitance : 78.5936;
|
||||
min_capacitance : 2.45605;
|
||||
memory_read(){
|
||||
address : ADDR;
|
||||
}
|
||||
pin(DATA[1:0]){
|
||||
pin(DOUT[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
@@ -130,26 +134,26 @@ cell (sram_2_16_1_scn3me_subm){
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk";
|
||||
timing_type : falling_edge;
|
||||
timing_type : rising_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.458, 0.504, 0.871",\
|
||||
"0.461, 0.506, 0.874",\
|
||||
"0.5, 0.544, 0.912");
|
||||
values("0.928, 0.959, 1.113",\
|
||||
"0.931, 0.962, 1.116",\
|
||||
"0.985, 1.018, 1.176");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("0.573, 0.649, 1.251",\
|
||||
"0.577, 0.652, 1.254",\
|
||||
"0.618, 0.69, 1.29");
|
||||
values("11.214, 11.27, 11.756",\
|
||||
"11.22, 11.27, 11.761",\
|
||||
"11.268, 11.323, 11.809");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.153, 0.233, 1.085",\
|
||||
"0.154, 0.234, 1.084",\
|
||||
"0.158, 0.237, 1.084");
|
||||
values("0.599, 0.624, 0.968",\
|
||||
"0.599, 0.623, 0.97",\
|
||||
"0.598, 0.623, 0.967");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.276, 0.356, 1.5",\
|
||||
"0.277, 0.357, 1.5",\
|
||||
"0.278, 0.363, 1.5");
|
||||
values("11.157, 11.165, 11.446",\
|
||||
"11.159, 11.162, 1.271",\
|
||||
"11.158, 11.165, 11.47");
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -298,19 +302,19 @@ cell (sram_2_16_1_scn3me_subm){
|
||||
internal_power(){
|
||||
when : "!CSb & clk & !WEb";
|
||||
rise_power(scalar){
|
||||
values("4.42361814306");
|
||||
values("2.033783461111111");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("4.42361814306");
|
||||
values("2.033783461111111");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb & !clk & WEb";
|
||||
rise_power(scalar){
|
||||
values("4.97118480973");
|
||||
values("2.032705683333334");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("4.97118480973");
|
||||
values("2.032705683333334");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
@@ -326,20 +330,20 @@ cell (sram_2_16_1_scn3me_subm){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk;
|
||||
rise_constraint(scalar) {
|
||||
values("1.875");
|
||||
values("9.6875");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("1.875");
|
||||
values("9.6875");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk;
|
||||
rise_constraint(scalar) {
|
||||
values("3.75");
|
||||
values("19.375");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("3.75");
|
||||
values("19.375");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
+133
-56
@@ -59,33 +59,78 @@ class openram_test(unittest.TestCase):
|
||||
# Reset the static duplicate name checker for unit tests.
|
||||
import hierarchy_design
|
||||
hierarchy_design.hierarchy_design.name_map=[]
|
||||
|
||||
|
||||
def check_golden_data(self, data, golden_data, error_tolerance=1e-2):
|
||||
"""
|
||||
This function goes through two dictionaries, key by key and compares
|
||||
each item. It uses relative comparisons for the items and returns false
|
||||
if there is a mismatch.
|
||||
"""
|
||||
|
||||
# Check each result
|
||||
data_matches = True
|
||||
for k in data.keys():
|
||||
if type(data[k])==list:
|
||||
for i in range(len(data[k])):
|
||||
if not self.isclose(k,data[k][i],golden_data[k][i],error_tolerance):
|
||||
data_matches = False
|
||||
else:
|
||||
self.isclose(k,data[k],golden_data[k],error_tolerance)
|
||||
if not data_matches:
|
||||
import pprint
|
||||
data_string=pprint.pformat(data)
|
||||
debug.error("Results exceeded {:.1f}% tolerance compared to golden results:\n".format(error_tolerance*100)+data_string)
|
||||
return data_matches
|
||||
|
||||
|
||||
|
||||
def isclose(self, value1,value2,error_tolerance=1e-2):
|
||||
def isclose(self,key,value,actual_value,error_tolerance=1e-2):
|
||||
""" This is used to compare relative values. """
|
||||
import debug
|
||||
relative_diff = abs(value1 - value2) / max(value1,value2)
|
||||
relative_diff = self.relative_diff(value,actual_value)
|
||||
check = relative_diff <= error_tolerance
|
||||
if not check:
|
||||
self.fail("NOT CLOSE {0} {1} relative diff={2}".format(value1,value2,relative_diff))
|
||||
else:
|
||||
debug.info(2,"CLOSE {0} {1} relative diff={2}".format(value1,value2,relative_diff))
|
||||
|
||||
def relative_compare(self, value1,value2,error_tolerance):
|
||||
""" This is used to compare relative values. """
|
||||
if (value1==value2): # if we don't need a relative comparison!
|
||||
if check:
|
||||
debug.info(2,"CLOSE\t{0: <10}\t{1:.3f}\t{2:.3f}\tdiff={3:.1f}%".format(key,value,actual_value,relative_diff*100))
|
||||
return True
|
||||
return (abs(value1 - value2) / max(value1,value2) <= error_tolerance)
|
||||
else:
|
||||
debug.error("NOT CLOSE\t{0: <10}\t{1:.3f}\t{2:.3f}\tdiff={3:.1f}%".format(key,value,actual_value,relative_diff*100))
|
||||
return False
|
||||
|
||||
def isapproxdiff(self, f1, f2, error_tolerance=0.001):
|
||||
def relative_diff(self, value1, value2):
|
||||
""" Compute the relative difference of two values and normalize to the largest.
|
||||
If largest value is 0, just return the difference."""
|
||||
|
||||
# Edge case to avoid divide by zero
|
||||
if value1==0 and value2==0:
|
||||
return 0.0
|
||||
|
||||
# Don't need relative, exact compare
|
||||
if value1==value2:
|
||||
return 0.0
|
||||
|
||||
# Get normalization value
|
||||
norm_value = abs(max(value1, value2))
|
||||
# Edge case where greater is a zero
|
||||
if norm_value == 0:
|
||||
min_value = abs(min(value1, value2))
|
||||
|
||||
return abs(value1 - value2) / norm_value
|
||||
|
||||
|
||||
def relative_compare(self, value,actual_value,error_tolerance):
|
||||
""" This is used to compare relative values. """
|
||||
if (value==actual_value): # if we don't need a relative comparison!
|
||||
return True
|
||||
return (abs(value - actual_value) / max(value,actual_value) <= error_tolerance)
|
||||
|
||||
def isapproxdiff(self, filename1, filename2, error_tolerance=0.001):
|
||||
"""Compare two files.
|
||||
|
||||
Arguments:
|
||||
|
||||
f1 -- First file name
|
||||
filename1 -- First file name
|
||||
|
||||
f2 -- Second file name
|
||||
filename2 -- Second file name
|
||||
|
||||
Return value:
|
||||
|
||||
@@ -106,61 +151,93 @@ class openram_test(unittest.TestCase):
|
||||
(?: [Ee] [+-]? \d+ ) ?
|
||||
"""
|
||||
rx = re.compile(numeric_const_pattern, re.VERBOSE)
|
||||
with open(f1, 'rb') as fp1, open(f2, 'rb') as fp2:
|
||||
while True:
|
||||
b1 = fp1.readline().decode('utf-8')
|
||||
b2 = fp2.readline().decode('utf-8')
|
||||
#print "b1:",b1,
|
||||
#print "b2:",b2,
|
||||
fp1 = open(filename1, 'rb')
|
||||
fp2 = open(filename2, 'rb')
|
||||
mismatches=0
|
||||
line_num=0
|
||||
while True:
|
||||
line_num+=1
|
||||
line1 = fp1.readline().decode('utf-8')
|
||||
line2 = fp2.readline().decode('utf-8')
|
||||
#print("line1:",line1)
|
||||
#print("line2:",line2)
|
||||
|
||||
# 1. Find all of the floats using a regex
|
||||
line1_floats=rx.findall(line1)
|
||||
line2_floats=rx.findall(line2)
|
||||
debug.info(3,"line1_floats: "+str(line1_floats))
|
||||
debug.info(3,"line2_floats: "+str(line2_floats))
|
||||
|
||||
# 1. Find all of the floats using a regex
|
||||
b1_floats=rx.findall(b1)
|
||||
b2_floats=rx.findall(b2)
|
||||
debug.info(3,"b1_floats: "+str(b1_floats))
|
||||
debug.info(3,"b2_floats: "+str(b2_floats))
|
||||
|
||||
# 2. Remove the floats from the string
|
||||
for f in b1_floats:
|
||||
b1=b1.replace(f,"",1)
|
||||
for f in b2_floats:
|
||||
b2=b2.replace(f,"",1)
|
||||
#print "b1:",b1,
|
||||
#print "b2:",b2,
|
||||
|
||||
# 3. Check if remaining string matches
|
||||
if b1 != b2:
|
||||
self.fail("MISMATCH Line: {0}\n!=\nLine: {1}".format(b1,b2))
|
||||
# 2. Remove the floats from the string
|
||||
for f in line1_floats:
|
||||
line1=line1.replace(f,"",1)
|
||||
for f in line2_floats:
|
||||
line2=line2.replace(f,"",1)
|
||||
#print("line1:",line1)
|
||||
#print("line2:",line2)
|
||||
|
||||
# 4. Now compare that the floats match
|
||||
if len(b1_floats)!=len(b2_floats):
|
||||
self.fail("MISMATCH Length {0} != {1}".format(len(b1_floats),len(b2_floats)))
|
||||
for (f1,f2) in zip(b1_floats,b2_floats):
|
||||
if not self.relative_compare(float(f1),float(f2),error_tolerance):
|
||||
self.fail("MISMATCH Float {0} != {1}".format(f1,f2))
|
||||
# 3. Convert to floats rather than strings
|
||||
line1_floats = [float(x) for x in line1_floats]
|
||||
line2_floats = [float(x) for x in line1_floats]
|
||||
|
||||
# 4. Check if remaining string matches
|
||||
if line1 != line2:
|
||||
if mismatches==0:
|
||||
debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1,filename2))
|
||||
mismatches += 1
|
||||
debug.error("MISMATCH Line ({0}):\n{1}\n!=\n{2}".format(line_num,line1.rstrip('\n'),line2.rstrip('\n')))
|
||||
|
||||
if not b1 and not b2:
|
||||
return
|
||||
# 5. Now compare that the floats match
|
||||
elif len(line1_floats)!=len(line2_floats):
|
||||
if mismatches==0:
|
||||
debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1,filename2))
|
||||
mismatches += 1
|
||||
debug.error("MISMATCH Line ({0}) Length {1} != {2}".format(line_num,len(line1_floats),len(line2_floats)))
|
||||
else:
|
||||
for (float1,float2) in zip(line1_floats,line2_floats):
|
||||
relative_diff = self.relative_diff(float1,float2)
|
||||
check = relative_diff <= error_tolerance
|
||||
if not check:
|
||||
if mismatches==0:
|
||||
debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1,filename2))
|
||||
mismatches += 1
|
||||
debug.error("MISMATCH Line ({0}) Float {1} != {2} diff: {3:.1f}%".format(line_num,float1,float2,relative_diff*100))
|
||||
|
||||
# Only show the first 10 mismatch lines
|
||||
if not line1 and not line2 or mismatches>10:
|
||||
fp1.close()
|
||||
fp2.close()
|
||||
return mismatches==0
|
||||
|
||||
# Never reached
|
||||
return False
|
||||
|
||||
|
||||
|
||||
def isdiff(self,file1,file2):
|
||||
def isdiff(self,filename1,filename2):
|
||||
""" This is used to compare two files and display the diff if they are different.. """
|
||||
import debug
|
||||
import filecmp
|
||||
import difflib
|
||||
check = filecmp.cmp(file1,file2)
|
||||
check = filecmp.cmp(filename1,filename2)
|
||||
if not check:
|
||||
debug.info(2,"MISMATCH {0} {1}".format(file1,file2))
|
||||
f1 = open(file1,"r")
|
||||
s1 = f1.readlines()
|
||||
f2 = open(file2,"r")
|
||||
debug.error("MISMATCH file1={0} file2={1}".format(filename1,filename2))
|
||||
f1 = open(filename1,"r")
|
||||
s1 = f1.readlines().decode('utf-8')
|
||||
f1.close()
|
||||
f2 = open(filename2,"r").decode('utf-8')
|
||||
s2 = f2.readlines()
|
||||
f2.close()
|
||||
mismatches=0
|
||||
for line in difflib.unified_diff(s1, s2):
|
||||
debug.info(3,line)
|
||||
self.fail("MISMATCH {0} {1}".format(file1,file2))
|
||||
mismatches += 1
|
||||
self.error("DIFF LINES:",line)
|
||||
if mismatches>10:
|
||||
return False
|
||||
return False
|
||||
else:
|
||||
debug.info(2,"MATCH {0} {1}".format(file1,file2))
|
||||
|
||||
debug.info(2,"MATCH {0} {1}".format(filename1,filename2))
|
||||
return True
|
||||
|
||||
def header(filename, technology):
|
||||
# Skip the header for gitlab regression
|
||||
|
||||
Reference in New Issue
Block a user