Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport

compiler/modules/control_logic.py

@@ -61,7 +61,9 @@ class control_logic(design.design):
         self.add_mod(self.nand3)
 
         # Special gates: inverters for buffering
-        self.clkbuf = pinvbuf(4,16,height=dff_height)
+        # Size the clock for the number of rows (fanout)
+        clock_driver_size = max(1,int(self.num_rows/4))
+        self.clkbuf = pinvbuf(clock_driver_size,height=dff_height)
         self.add_mod(self.clkbuf)
         self.inv = self.inv1 = pinv(size=1, height=dff_height)
         self.add_mod(self.inv1)
@@ -345,7 +347,7 @@ class control_logic(design.design):
         x_off = self.ctrl_dff_inst.width + self.internal_bus_width
         (y_off,mirror)=self.get_offset(row)
             
-        # input: WE, clk_buf_bar, CS output: w_en_bar
+        # input: WE, CS output: w_en_bar
         w_en_bar_offset = vector(x_off, y_off)
         self.w_en_bar_inst=self.add_inst(name="nand3_w_en_bar",
                                          mod=self.nand3,

compiler/modules/dff_buf.py

@@ -20,6 +20,12 @@ class dff_buf(design.design):
         design.design.__init__(self, name)
         debug.info(1, "Creating {}".format(self.name))
 
+        # This is specifically for SCMOS where the DFF vdd/gnd rails are more than min width.
+        # This causes a DRC in the pinv which assumes min width rails. This ensures the output
+        # contact does not violate spacing to the rail in the NMOS.
+        debug.check(inv1_size>=2, "Inverter must be greater than two for rail spacing DRC rules.")
+        debug.check(inv2_size>=2, "Inverter must be greater than two for rail spacing DRC rules.")        
+
         from importlib import reload
         c = reload(__import__(OPTS.dff))
         self.mod_dff = getattr(c, OPTS.dff)

compiler/modules/dff_inv.py

@@ -12,19 +12,24 @@ class dff_inv(design.design):
     do not have Qbar, so this will create it.
     """
 
-    def __init__(self, inv_size=1, name=""):
+    def __init__(self, inv_size=2, name=""):
 
         if name=="":
             name = "dff_inv_{0}".format(inv_size)
         design.design.__init__(self, name)
         debug.info(1, "Creating {}".format(self.name))
 
+        # This is specifically for SCMOS where the DFF vdd/gnd rails are more than min width.
+        # This causes a DRC in the pinv which assumes min width rails. This ensures the output
+        # contact does not violate spacing to the rail in the NMOS.
+        debug.check(inv_size>=2, "Inverter must be greater than two for rail spacing DRC rules.")
+
         from importlib import reload
         c = reload(__import__(OPTS.dff))
         self.mod_dff = getattr(c, OPTS.dff)
         self.dff = self.mod_dff("dff")
         self.add_mod(self.dff)
-
+        
         self.inv1 = pinv(size=inv_size,height=self.dff.height)
         self.add_mod(self.inv1)
 

compiler/modules/wordline_driver.py

@@ -127,14 +127,14 @@ class wordline_driver(design.design):
                                                 mirror=inst_mirror))
             self.connect_inst(["en_bar[{0}]".format(row),
                                "in[{0}]".format(row),
-                               "net[{0}]".format(row),
+                               "wl_bar[{0}]".format(row),
                                "vdd", "gnd"])
             # add inv2
             self.inv2_inst.append(self.add_inst(name=name_inv2,
                                                 mod=self.inv,
                                                 offset=inv2_offset,
                                                 mirror=inst_mirror))
-            self.connect_inst(["net[{0}]".format(row),
+            self.connect_inst(["wl_bar[{0}]".format(row),
                                "wl[{0}]".format(row),
                                "vdd", "gnd"])