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Allow 16-way column mux

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This commit is contained in:
mrg
2020-10-06 16:27:02 -07:00
parent 27d921d2db
commit c2629edc1b
5 changed files with 53 additions and 48 deletions
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compiler/modules/bank.py
+3
View File
@@ -533,6 +533,9 @@ class bank(design.design):
elif self.col_addr_size == 3:
self.column_decoder = factory.create(module_type="hierarchical_predecode3x8",
height=self.dff.height)
elif self.col_addr_size == 4:
self.column_decoder = factory.create(module_type="hierarchical_predecode4x16",
height=self.dff.height)
else:
# No error checking before?
debug.error("Invalid column decoder?", -1)
compiler/modules/port_address.py
+2 -2
View File
@@ -79,8 +79,8 @@ class port_address(design.design):
self.copy_power_pins(inst, "vdd")
self.copy_power_pins(inst, "gnd")
rbl_vdd_pin = self.rbl_driver_inst.get_pin("vdd")
self.add_power_pin("vdd", rbl_vdd_pin.lc())
for rbl_vdd_pin in self.rbl_driver_inst.get_pins("vdd"):
self.add_power_pin("vdd", rbl_vdd_pin.center())
def route_pins(self):
for row in range(self.addr_size):
compiler/modules/replica_column.py
+4 -2
View File
@@ -221,8 +221,10 @@ class replica_column(bitcell_base_array):
bitcell_pins = []
for port in self.all_ports:
bitcell_pins.extend([x for x in self.get_bitline_names(port) if x.endswith("_{0}".format(col))])
bitcell_pins.append("vdd")
bitcell_pins.append("gnd")
if len(self.edge_cell.get_pins("vdd")) > 0:
bitcell_pins.append("vdd")
if len(self.edge_cell.get_pins("gnd")) > 0:
bitcell_pins.append("gnd")
return bitcell_pins